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Cypress CY7C67200 manual Watchdog Timer Register 0xC00C R/W, Lock, Strobe

Models: CY7C67200

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Watchdog Timer Register [0xC00C] [R/W]

CY7C67200

Watchdog Timer Register [0xC00C] [R/W]

Figure 15. Watchdog Timer Register

Bit #	15	14	13	12	11	10	9	8
Field				Reserved...
Read/Write	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field	...Reserved		Timeout	Period			Lock	WDT	Reset
Field			Flag	Select			Enable	Enable	Strobe
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	W
Default	0	0	0	0		0	0	0	0

Register Description

The Watchdog Timer register provides status and control over the Watchdog timer. The Watchdog timer can also interrupt the processor.

Timeout Flag (Bit 5)

The Timeout Flag bit indicates if the Watchdog timer has expired. The processor can read this bit after exiting a reset to determine if a Watchdog timeout occurred. This bit is cleared on the next external hardware reset.

1:Watchdog timer expired

0:Watchdog timer did not expire

Period Select (Bits [4:3])

The Period Select field is defined in Table 21. If this time expires before the Reset Strobe bit is set, the internal processor is reset.

Table 21.Period Select Definition

Period Select[4:3]	WDT Period Value
00	1.4 ms
01	5.5 ms
10	22.0 ms
11	66.0 ms

Lock Enable (Bit 2)

The Lock Enable bit does not allow any writes to this register until a reset. In doing so the Watchdog timer can be set up and enabled permanently so that it can only be cleared on reset (the WDT Enable bit is ignored).

1:Watchdog timer permanently set

0:Watchdog timer not permanently set

WDT Enable (Bit 1)

The WDT Enable bit enables or disables the Watchdog timer.

1:Enable Watchdog timer operation

0:Disable Watchdog timer operation

Reset Strobe (Bit 0)

The Reset Strobe is a write-only bit that resets the Watchdog timer count. It must be set to ‘1’ before the count expires to avoid a Watchdog trigger

1:Reset Count

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Watchdog Timer Register 0xC00C R/W, Lock, Strobe

Contents

CY7C67200 EZ-OTG FeaturesTypical Applications CY7C67200Processor Core Functional Overview IntroductionInterface Descriptions CY7C67200USB Pins USB FeaturesOTG Features OTG PinsUART Pins UART FeaturesI2C EEPROM Features I2C EEPROM PinsHPI Pins HPI FeaturesCY7C67200 CY7C67200Charge Pump Pins Charge Pump FeaturesBooster Pins CY7C67200Coprocessor Mode Crystal PinsStandalone Mode CY7C67200Minimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings and Reset DescriptionFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionMemory Map LCP Variables USB Registers Slave Setup Packet BIOS StackInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCY7C67200 RegistersCPU Flags Register 0xC000 R CY7C67200 Bank Register 0xC002 R/WHardware Revision Register 0xC004 R CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WCY7C67200 USB Diagnostic Register 0xC03C R/WPull-down Force SelectCY7C67200 Watchdog Timer Register 0xC00C R/WLock StrobeUSB n Control Register R/W Timer n Register R/WResistors Enable CY7C67200Pull up/Pull down on D+ and CY7C672000xC090/0xC0B0 0xC094/0xC0B4CY7C67200 Host n Control Register R/WSequence SyncCY7C67200 Host n Address Register R/WHost n Count Register R/W Length Host n Endpoint Status Register RCY7C67200 CY7C67200 Host n PID Register WCY7C67200 Host n Count Result Register RHost n Device Address Register W Port A Connect Host n Interrupt Enable Register R/WCY7C67200 Port A Connect Host n Status Register R/WCY7C67200 CY7C67200 Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R CY7C67200 Host n Frame Register RDevice n Endpoint n Control Register R/W CY7C67200 CY7C67200 Device n Endpoint n Address Register R/WDevice n Endpoint n Count Register R/W CY7C67200 Device n Endpoint n Status Register R/WSetup Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WCY7C67200 Device n Interrupt Enable Register R/WInterrupt Enable Page 35 of CY7C67200CY7C67200 Device n Address Register WDevice n Status Register R/W Page 37 of CY7C67200CY7C67200 Device n Frame Number Register RDevice n SOF/EOP Count Register W C098H OTG Control Register 0xC098 R/WCY7C67200 CY7C67200 GPIO Control Register 0xC006 R/WCY7C67200 GPIO 0 Output Data Register 0xC01E R/WGPIO 1 Output Data Register 0xC024 R/W GPIO 1 Input Data Register 0xC026 R GPIO 0 Input Data Register 0xC020 RGPIO 0 Direction Register 0xC022 R/W CY7C67200CY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WCY7C67200 HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W CY7C67200 HSS Receive Address Register 0xC078 R/WHSS Receive Counter Register 0xC07A R/W CY7C67200 HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W CY7C67200 HPI Breakpoint Register 0x0140 RInterrupt Routing Register 0x0142 R CY7C67200 SOF/EOP2 to CPU Enable BitCY7C67200 SIEXmsg Register WHPI Mailbox Register 0xC0C6 R/W CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitCY7C67200 SPI Control Register 0xC0CA R/WStrobe Receive Bit LengthCY7C67200 SPI Interrupt Enable Register 0xC0CC R/WSPI Status Register 0xC0CE R CY7C67200 SPI Interrupt Clear Register 0xC0D0 WSPI CRC Control Register 0xC0D2 R/W CY7C67200 SPI CRC Value Register 0xC0D4 R/WSPI Data Register 0xC0D6 R/W CY7C67200 SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register 0xC0DA R/W CY7C67200 SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W CY7C67200 UART Control Register 0xC0E0 R/WUART Status Register 0xC0E2 R CY7C67200 UART Data Register 0xC0E4 R/WCY7C67200 Pin DiagramPin Descriptions Table 38.Pin Descriptions continued CY7C67200Name TypeOperating Conditions Absolute Maximum RatingsCrystal Requirements XTALIN, XTALOUT CY7C67200CY7C67200 DC CharacteristicsReset Timing AC Timing CharacteristicsnRESET nRD or nWRL or nWRH CY7C672001. I2C EEPROM Bus Timing - Serial I/O Clock TimingXTALIN CY7C67200CY7C67200 ADDR nCS nWR nRD DouttASU tCSSU tCYCCY7C67200 ADDRHSS BYTE Mode Transmit CY7C67200HSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceivePage 72 of CY7C67200Hardware CTS/RTS Handshake Default High Register SummaryDefault Low CY7C67200Default Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackOrdering Information Package DiagramCY7C67200 Table 43.Ordering Information“Interrupt Enable Register 0xC00E R/W” Document History PageCY7C67200 Mode”