Cypress CY7C67200 manual Device n Endpoint n Address Register R/W

CY7C67200

Device n Endpoint n Address Register [R/W]

•Device n Endpoint 0 Address Register [Device 1: 0x0202 Device 2: 0x0282]

•Device n Endpoint 1 Address Register [Device 1: 0x0212 Device 2: 0x0292]

•Device n Endpoint 2 Address Register [Device 1: 0x0222 Device 2: 0x02A2]

•Device n Endpoint 3 Address Register [Device 1: 0x0232 Device 2: 0x02B2]

•Device n Endpoint 4 Address Register [Device 1: 0x0242 Device 2: 0x02C2]

•Device n Endpoint 5 Address Register [Device 1: 0x0252 Device 2: 0x02D2]

•Device n Endpoint 6 Address Register [Device 1: 0x0262 Device 2: 0x02E2]

•Device n Endpoint 7 Address Register [Device 1: 0x0272 Device 2: 0x02F2]

Figure 31. Device n Endpoint n Address Register

Bit #	15	14	13	12		11	10	9	8
Field					Address...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	X	X	X	X		X	X	X	X

Bit #	7	6	5	4		3	2	1	0
Field					...Address
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	X	X	X	X		X	X	X	X

Register Description

The Device n Endpoint n Address register is used as the base pointer into memory space for the current Endpoint transaction. There are a total of eight endpoints for each of the two ports. All endpoints have the same definition for their Device n Endpoint n Address register.

Address (Bits [15:0])

The Address field sets the base address for the current transaction on a signal endpoint.

Device n Endpoint n Count Register [R/W]

•Device n Endpoint 0 Count Register [Device 1: 0x0204 Device 2: 0x0284]

•Device n Endpoint 1 Count Register [Device 1: 0x0214 Device 2: 0x0294]

•Device n Endpoint 2 Count Register [Device 1: 0x0224 Device 2: 0x02A4]

•Device n Endpoint 3 Count Register [Device 1: 0x0234 Device 2: 0x02B4]

•Device n Endpoint 4 Count Register [Device 1: 0x0244 Device 2: 0x02C4]

•Device n Endpoint 5 Count Register [Device 1: 0x0254 Device 2: 0x02D4]

•Device n Endpoint 6 Count Register [Device 1: 0x0264 Device 2: 0x02E4]

•Device n Endpoint 7 Count Register [Device 1: 0x0274 Device 2: 0x02F4]

Figure 32. Device n Endpoint n Count Register

Bit #	15	14	13		12	11	10	9		8
Field				Reserved					Count...
Read/Write	-	-	-		-	-	-	R/W		R/W
Default	X	X	X		X	X	X	X		X

Bit #	7	6	5	4		3	2	1	0
Field					...Count
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	X	X	X	X		X	X	X	X

Document #: 38-08014 Rev. *G Page 30 of 78

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