CRC Enable Bit, CRC Clear Bit, Receive CRC Bit | Cypress CY7C67200

CY7C67200

CRC Enable (Bit 13)

The CRC Enable bit enables or disables the CRC operation.

1:Enables CRC operation

0:Disables CRC operation

CRC Clear (Bit 12)

The CRC Clear bit will clear the CRC with a load of all ones. This bit is self clearing and always reads ‘0’.

1:Clear CRC with all ones

0:No Function

Receive CRC (Bit 11)

The Receive CRC bit determines whether the receive bit stream or the transmit bit stream is used for the CRC data input in full duplex mode. This bit is a don’t care in half-duplex mode.

1:Assigns the receive bit stream

0:Assigns the transmit bit stream

SPI CRC Value Register [0xC0D4] [R/W]

One in CRC (Bit 10)

The One in CRC bit is a read-only bit that indicates if the CRC value is all zeros or not.

1:CRC value is not all zeros

0:CRC value is all zeros

Zero in CRC (Bit 9)

The Zero in CRC bit is a read-only bit that indicates if the CRC value is all ones or not.

1:CRC value is not all ones

0:CRC value is all ones

Reserved

All reserved bits must be written as ‘0’.

Figure 67. SPI CRC Value Register

Bit #	15	14	13	12		11	10	9	8
Field					CRC...
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	1	1	1	1		1	1	1	1

Bit #	7	6	5	4		3	2	1	0
Field					...CRC
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	1	1	1	1		1	1	1	1

Register Description

The SPI CRC Value register contains the CRC value.

CRC (Bits [15:0])

The CRC field contains the SPI CRC. In CRC Mode CRC7, the CRC value will be a seven bit value [6:0]. Therefore bits [15:7] are invalid in CRC7 mode.

SPI Data Register [0xC0D6] [R/W]

Figure 68. SPI Data Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	X	X	X	X		X	X	X	X

Bit #	7	6	5	4		3	2	1	0
Field					Data
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	X	X	X	X		X	X	X	X

Register Description

The SPI Data register contains data received on the SPI port when read. Reading it empties the eight byte receive FIFO in PIO byte mode. This receive data is valid when the receive bit of the SPI Interrupt Value is set to ‘1’ (RxIntVal triggers) or the Receive

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual CRC Enable Bit, CRC Clear Bit, Receive CRC Bit, One in CRC Bit, Zero in CRC Bit

Contents

CY7C67200 EZ-OTG FeaturesTypical Applications CY16 Processor Core Functional Overview IntroductionInterface Descriptions USB Interface USB Interface Pins Pin Name Pin NumberOTG Interface Pins Pin Name Pin Number OTG Interface HSS Interface Pins Pin Name Pin Number I2C Eeprom Interface Pins Pin Name Pin NumberSPI Interface Pins Pin Name Pin Number Serial Peripheral Interface HPI Addressing HPI A10 HPI Interface Pins 1 Pin Name Pin NumberHost Port Interface HPI Charge Pump Interface Booster Interface Charge Pump Interface Pins Pin Name Pin NumberCrystal Interface Boot Mode Crystal Pins Pin Name Pin NumberBoot Configuration Interface Pin Power Savings Mode Description Power Savings and Reset DescriptionSleep Memory Map Registers Reserved Bank Register 0xC002 R/WBank Register Example Hex Value Binary Value Hardware Revision Register 0xC004 R CPU Speed Register 0xC008 R/W CPU Speed Definition Processor Speed OTG Wake Enable Bit Host/Device 2 Wake Enable BitHost/Device 1 Wake Enable Bit HSS Wake Enable Bit SPI Interrupt Enable Bit Halt Enable BitOTG Interrupt Enable Bit Host/Device 2 Interrupt Enable Bit Timer 1 Interrupt Enable Bit Uart Interrupt Enable BitGpio Interrupt Enable Bit Timer 0 Interrupt Enable Bit Pull-down Enable Bit Port 2A Diagnostic Enable BitPort 1A Diagnostic Enable Bit LS Pull-up Enable Bit WDT Enable Bit Timeout Flag BitLock Enable Bit Reset Strobe Bit USB Registers Register Name Address SIE1/SIE2 Timer n Register R/WGeneral USB Registers 0xC08A/0xC0AA USB Data Line Pull-up and Pull-down Resistors Mode Port n Mode Select BitPort a Resistors Enable Bit Resistors Function Select Enable ISO Enable Bit Preamble Enable BitSync Enable Bit Arm Enable Bit Host n Count Register R/W Host n Address Register R/WHost 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Stall Flag Bit Error Flag BitUnderflow Flag Bit NAK Flag Bit PID Select Definition ACK Flag BitHost n PID Register W PID Select Host n Count Result Register R Host n Device Address Register W SOF/EOP Interrupt Enable Bit Vbus Interrupt Enable BitID Interrupt Enable Bit Port a Wake Interrupt Enable Bit SOF/EOP Interrupt Flag Bit Vbus Interrupt Flag BitID Interrupt Flag Bit Port a Wake Interrupt Flag Bit Count Bits Count field sets the SOF/EOP counter duration Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R USB Device Only Registers Host n Frame Register RUSB Device Only Registers Reserved Register Name Address Device 1/Device NAK Interrupt Enable Bit IN/OUT Ignore Enable BitStall Enable Bit Enable Bit Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/W Device n Endpoint n Status Register R/W OUT Exception Flag Bit Error occurred Error did not occur Setup Flag BitTimeout occurred Timeout condition did not occur Exception Flag Bit Device n Endpoint n Count Result Register R/W Device n Endpoint n Count Result Register Reset Interrupt Enable Bit Device n Interrupt Enable Register R/WSOF/EOP Timeout Interrupt Enable Bit EP7 Interrupt Enable Bit EP3 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable BitEP4 Interrupt Enable Bit EP1 Interrupt Enable Bit Device n Address Register W Device n Status Register R/W EP6 Interrupt Flag Bit Reset Interrupt Flag BitEP7 Interrupt Flag Bit EP5 Interrupt Flag Bit Device n Frame Number Register R SOF/EOP Timeout Flag BitSOF/EOP Timeout Interrupt Counter Bits Device n SOF/EOP Count Register W Charge Pump Enable Bit Vbus Pull-up Enable BitReceive Disable Bit Vbus Discharge Enable Bit Mode Select Definition Gpio Configuration 108 111 Reserved Write Protect Enable BitSAS Enable Bit Vbus Valid Flag Bit Interrupt 0 Enable Bit HSS Enable BitSPI Enable Bit Interrupt 0 Polarity Select Bit Gpio 1 Input Data Register 0xC026 R Gpio 0 Input Data Register 0xC020 RGpio 0 Direction Register 0xC022 R/W HSS Registers Gpio 1 Direction Register 0xC028 R/WHSS Registers Register Name Address Receive Interrupt Enable Bit Xoff Enable BitCTS Enable Bit RTS Polarity Select Bit Receive Overflow Flag Bit Packet Mode Select BitTransmit Ready Bit Receive Packet Ready Flag Bit Transmit Gap Select Bits HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/W HPI Registers HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W HPI Registers Register Name Address SOF/EOP2 to HPI Enable Bit Vbus to HPI Enable BitID to HPI Enable Bit HPI Breakpoint Register 0x0140 R SOF/EOP1 to CPU Enable Bit SOF/EOP2 to CPU Enable BitSOF/EOP1 to HPI Enable Bit Reset2 to HPI Enable Bit Data Bits SIEXmsg Register WSIE1msg Register SIE2msg Register HPI Mailbox Register 0xC0C6 R/W ID Flag Bit Reset2 Flag BitVbus Flag Bit SOF/EOP2 Flag Bit Mailbox Out Flag Bit SPI Registers Reset1 Flag BitDone1 Flag Bit SPI Registers Register Name Address Master Active Enable Bit 3Wire Enable BitPhase Select Bit Master Enable Bit SCK Strobe Bit Byte Mode BitRead Enable Bit Fifo Init Bit Fifo Error Flag Bit Transmit Interrupt Enable BitTransfer Interrupt Enable Bit Receive Bit Length Bits Transfer Interrupt Flag Bit CRC Mode Definition CRCMode CRC PolynomialTransmit Interrupt Flag Bit Transmit Interrupt Clear Bit Receive CRC Bit CRC Enable BitCRC Clear Bit One in CRC Bit SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/W Uart Registers SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W Uart Registers Register Name Address Baud Select Bits Uart Enable BitScale Select Bit Uart Baud Select Definition Baud Rate DIV8 = Transmit Full Bit Uart Data Register 0xC0E4 R/W Pin Descriptions Pin DiagramPin Descriptions Name Type GPIO19 General Purpose IO GPIO20 General Purpose IOA1 HPI A1 A0 HPI A0 Operating Conditions Booster Power Input 2.7V toAbsolute Maximum Ratings Crystal Requirements XTALIN, Xtalout DC Characteristics AC Timing Characteristics Reset Timing I2C Eeprom Timing Clock TimingParameter Description Min Typical Max Unit HPI Host Port Interface Write Cycle Timing Read Pulse Width Data Access Time, from HPInRD fallingHPI Host Port Interface Read Cycle Timing Read Cycle Time Document # 38-08014 Rev. *G HSS Block Mode Transmit HSS Byte Mode TransmitHSS Byte and Block Mode Receive Hardware CTS/RTS Handshake Hssrts Hsscts Register Summary Register Summary GPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Ordering Information Ordering Code Package Type PB-Free Package DiagramOrdering Information Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Issue Orig. Description of Change Date Document History