Cypress CY7C67200 Clock Timing, I2C Eeprom Timing, Parameter Description Min Typical Max Unit

CY7C67200

Clock Timing

tCLK

XTALIN

tHIGH

tLOW

tFALL

tRISE

Clock Timing

Parameter	Description	Min.	Typ.	Max.	Unit
fCLK	Clock Frequency		12.0		MHz
vXINH[10]	Clock Input High	1.5	3.0	3.6	V
	(XTALOUT left floating)
tCLK	Clock Period	83.17	83.33	83.5	ns
tHIGH	Clock High Time	36		44	ns
tLOW	Clock Low Time	36		44	ns
tRISE	Clock Rise Time			5.0	ns
tFALL	Clock Fall Time			5.0	ns
Duty Cycle		45		55	%

I2C EEPROM Timing

1. I2C EEPROM Bus Timing - Serial I/O

SCL
tSU.STA	tHD.STA
SDA IN
		tAA

tLOW			tHIGH		tR
	tHD.DAT			tSU.DAT
		tDH

tF

tSU.STO tBUF

	SDA OUT
	Parameter	Description	Min.	Typical	Max.	Unit
	fSCL	Clock Frequency			400	kHz
	tLOW	Clock Pulse Width Low	1300			ns
	tHIGH	Clock Pulse Width High	600			ns
	tAA	Clock Low to Data Out Valid	900			ns
	tBUF	Bus Idle Before New Transmission	1300			ns
	tHD.STA	Start Hold Time	600			ns
	tSU.STA	Start Setup Time	600			ns
	tHD.DAT	Data In Hold Time	0			ns
	tSU.DAT	Data In Setup Time	100			ns
	tR	Input Rise Time			300	ns
	tF	Input Fall Time			300	ns
	tSU.STO	Stop Setup Time	600			ns
	tDH	Data Out Hold Time	0			ns
	Note
	10. vXINH is required to be 3.0V to obtain an internal 50/50 duty cycle clock.
Document #: 38-08014 Rev. *G						Page 68 of 78

[+] Feedback