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Cypress CY7C67200 manual Host n Count Result Register R, Host n Device Address Register W

Models: CY7C67200

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Host n Count Result Register [R]

CY7C67200

Host n Count Result Register [R]

•Host 1 Count Result Register 0xC088

•Host 2 Count Result Register 0xC0A8

Figure 23. Host n Count Result Register

Bit #	15	14	13	12		11	10	9	8
Field					Result...
Read/Write	R	R	R	R		R	R	R	R
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					...Result
Read/Write	R	R	R	R		R	R	R	R
Default	0	0	0	0		0	0	0	0

Register Description

The Host n Count Result register is a read-only register that contains the size difference in bytes between the Host Count Value specified in the Host n Count register and the last packet received. If an overflow or underflow condition occurs, that is the received packet length differs from the value specified in the Host n Count register, the Length Exception Flag bit in the Host n Endpoint Status register will be set. The value in this register is only valid when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Host n Endpoint Status register.

Result (Bits [15:0])

The Result field contains the differences in bytes between the received packet and the value specified in the Host n Count register. If an overflow condition occurs, Result [15:10] is set to ‘111111’, a 2’s complement value indicating the additional byte count of the received packet. If an underflow condition occurs, Result [15:0] indicates the excess byte count (number of bytes not used).

Reserved

All reserved bits must be written as ‘0’.

Host n Device Address Register [W]

•Host 1 Device Address Register 0xC088

•Host 2 Device Address Register 0xC0A8

Figure 24. Host n Device Address Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved...
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	...Reserved				Address
Read/Write	-	W	W	W	W	W	W	W
Default	0	0	0	0	0	0	0	0

Register Description

The Host n Device Address register is a write-only register that contains the USB Device Address that the host wishes to communicate with.

Address (Bits [6:0])

The Address field contains the value of the USB address for the next device that the host is going to communicate with. This value must be written by firmware.

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Host n Count Result Register R, Host n Device Address Register W

Contents

EZ-OTG Features CY7C67200Typical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions CY7C67200USB Features USB PinsOTG Features OTG PinsUART Features UART PinsI2C EEPROM Features I2C EEPROM PinsHPI Features HPI PinsCY7C67200 CY7C67200Charge Pump Features Charge Pump PinsBooster Pins CY7C67200Crystal Pins Coprocessor ModeStandalone Mode CY7C67200Power Savings and Reset Description Minimum Hardware Requirements for Standalone Mode - Peripheral OnlyFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionLCP Variables USB Registers Slave Setup Packet BIOS Stack Memory MapInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FRegisters CPU Flags Register 0xC000 RCY7C67200 Bank Register 0xC002 R/W Hardware Revision Register 0xC004 RCY7C67200 CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200USB Diagnostic Register 0xC03C R/W CY7C67200Pull-down Force SelectWatchdog Timer Register 0xC00C R/W CY7C67200Lock StrobeTimer n Register R/W USB n Control Register R/WResistors Enable CY7C67200CY7C67200 Pull up/Pull down on D+ and0xC090/0xC0B0 0xC094/0xC0B4Host n Control Register R/W CY7C67200Sequence SyncHost n Address Register R/W Host n Count Register R/WCY7C67200 Host n Endpoint Status Register R CY7C67200Length Host n PID Register W CY7C67200Host n Count Result Register R Host n Device Address Register WCY7C67200 Host n Interrupt Enable Register R/W CY7C67200Port A Connect Host n Status Register R/W CY7C67200Port A Connect Host n SOF/EOP Count Register R/W Host n SOF/EOP Counter Register RCY7C67200 Host n Frame Register R Device n Endpoint n Control Register R/WCY7C67200 CY7C67200 Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WCY7C67200 Device n Endpoint n Status Register R/W SetupCY7C67200 CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200Device n Interrupt Enable Register R/W Interrupt EnableCY7C67200 CY7C67200 Page 35 ofDevice n Address Register W Device n Status Register R/WCY7C67200 CY7C67200 Page 37 ofDevice n Frame Number Register R Device n SOF/EOP Count Register WCY7C67200 OTG Control Register 0xC098 R/W CY7C67200C098H GPIO Control Register 0xC006 R/W CY7C67200GPIO 0 Output Data Register 0xC01E R/W GPIO 1 Output Data Register 0xC024 R/WCY7C67200 GPIO 0 Input Data Register 0xC020 R GPIO 1 Input Data Register 0xC026 RGPIO 0 Direction Register 0xC022 R/W CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200HSS Transmit Gap Register 0xC074 R/W HSS Data Register 0xC076 R/WCY7C67200 HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WCY7C67200 HSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WCY7C67200 HPI Breakpoint Register 0x0140 R Interrupt Routing Register 0x0142 RCY7C67200 SOF/EOP2 to CPU Enable Bit CY7C67200SIEXmsg Register W HPI Mailbox Register 0xC0C6 R/WCY7C67200 HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200SPI Control Register 0xC0CA R/W CY7C67200Strobe Receive Bit LengthSPI Interrupt Enable Register 0xC0CC R/W SPI Status Register 0xC0CE RCY7C67200 SPI Interrupt Clear Register 0xC0D0 W SPI CRC Control Register 0xC0D2 R/WCY7C67200 SPI CRC Value Register 0xC0D4 R/W SPI Data Register 0xC0D6 R/WCY7C67200 SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WCY7C67200 SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WCY7C67200 UART Control Register 0xC0E0 R/W UART Status Register 0xC0E2 RCY7C67200 UART Data Register 0xC0E4 R/W CY7C67200Pin Diagram Pin DescriptionsCY7C67200 CY7C67200 Table 38.Pin Descriptions continuedName TypeAbsolute Maximum Ratings Operating ConditionsCrystal Requirements XTALIN, XTALOUT CY7C67200DC Characteristics CY7C67200AC Timing Characteristics Reset TimingnRESET nRD or nWRL or nWRH CY7C67200Clock Timing 1. I2C EEPROM Bus Timing - Serial I/OXTALIN CY7C67200ADDR nCS nWR nRD Dout CY7C67200tASU tCSSU tCYCADDR CY7C67200CY7C67200 HSS BYTE Mode TransmitHSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceiveCY7C67200 Hardware CTS/RTS HandshakePage 72 of Register Summary Default HighDefault Low CY7C67200Default High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackPackage Diagram Ordering InformationCY7C67200 Table 43.Ordering InformationDocument History Page “Interrupt Enable Register 0xC00E R/W”CY7C67200 Mode”