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Cypress CY7C67200 manual GPIO Control Register 0xC006 R/W

Models: CY7C67200

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GPIO Control Register [0xC006] [R/W]

CY7C67200

VBUS Valid Flag (Bit 0)

The VBUS Valid Flag bit indicates whether OTG VBus is greater than 4.4V. After turning on VBUS, firmware should wait at least 10 µs before this reading this bit.

GPIO Registers

1:OTG VBus is greater then 4.4V

0:OTG VBus is less then 4.4V

Reserved

All reserved bits must be written as ‘0’.

There are seven registers dedicated for GPIO operations. These seven registers are covered in this section and summarized in Table 29.

Table 29.GPIO Registers

Register Name

Address

R/W

GPIO Control Register

0xC006

R/W

GPIO0 Output Data Register

0xC01E

R/W

GPIO0 Input Data Register

0xC020

R

GPIO0 Direction Register

0xC022

R/W

GPIO1 Output Data Register

0xC024

R/W

GPIO1 Input Data Register

0xC026

R

GPIO1 Direction Register

0xC028

R/W

GPIO Control Register [0xC006] [R/W]

Figure 41. GPIO Control Register

Bit #

15

14

13

12

11

10

9

8

Field

Write Protect

Reserved

Reserved

SAS

Mode

Enable

Enable

Select

Read/Write

R/W

-

R

-

R/W

R/W

R/W

R/W

Default

0

0

0

0

0

0

0

0

Bit #

7

6

5

4

3

2

1

0

Field

HSS

Reserved

SPI

Reserved

Interrupt 0

Interrupt 0

Enable

Enable

Polarity Select

Enable

Read/Write

R/W

-

R/W

-

-

-

R/W

R/W

Default

0

0

0

0

0

0

0

0

Register Description

The GPIO Control register configures the GPIO pins for various interface options. It also controls the polarity of the GPIO interrupt on IRQ0 (GPIO24).

Write Protect Enable (Bit 15)

The Write Protect Enable bit enables or disables the GPIO write protect. When Write Protect is enabled, the GPIO Mode Select [15:8] bits are read-only until a chip reset.

1:Enable Write Protect

0:Disable Write Protect

SAS Enable (Bit 11)

The SAS Enable bit, when in SPI mode, reroutes the SPI port SPI_nSSI pin to GPIO[15] rather then GPIO[9].

1:Reroute SPI_nss to GPIO[15]

0:Leave SPI_nss on GPIO[9]

Mode Select (Bits [10:8])

The Mode Select field selects how GPIO[15:0] and GPIO[24:19] are used as defined in Table 30.

Table 30.Mode Select Definition

	Mode Select	GPIO Configuration
	[10:8]	GPIO Configuration
	[10:8]
	111	Reserved

110SCAN – (HW) Scan diagnostic. For produc- tion test only. Not for normal operation

101HPI – Host Port Interface

100Reserved

011Reserved

010Reserved

001Reserved

000GPIO – General Purpose Input Output

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual GPIO Control Register 0xC006 R/W

Contents

EZ-OTG Features CY7C67200Typical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions CY7C67200USB Features USB PinsOTG Features OTG PinsUART Features UART PinsI2C EEPROM Features I2C EEPROM PinsHPI Features HPI PinsCY7C67200 CY7C67200Charge Pump Features Charge Pump PinsBooster Pins CY7C67200Crystal Pins Coprocessor ModeStandalone Mode CY7C67200Power Savings and Reset Description Minimum Hardware Requirements for Standalone Mode - Peripheral OnlyFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionLCP Variables USB Registers Slave Setup Packet BIOS Stack Memory MapInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCPU Flags Register 0xC000 R RegistersCY7C67200 Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WCY7C67200 CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200USB Diagnostic Register 0xC03C R/W CY7C67200Pull-down Force SelectWatchdog Timer Register 0xC00C R/W CY7C67200Lock StrobeTimer n Register R/W USB n Control Register R/WResistors Enable CY7C67200CY7C67200 Pull up/Pull down on D+ and0xC090/0xC0B0 0xC094/0xC0B4Host n Control Register R/W CY7C67200Sequence SyncHost n Count Register R/W Host n Address Register R/WCY7C67200 CY7C67200 Host n Endpoint Status Register RLength Host n PID Register W CY7C67200Host n Device Address Register W Host n Count Result Register RCY7C67200 CY7C67200 Host n Interrupt Enable Register R/WPort A Connect CY7C67200 Host n Status Register R/WPort A Connect Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCY7C67200 Device n Endpoint n Control Register R/W Host n Frame Register RCY7C67200 CY7C67200 Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WCY7C67200 Setup Device n Endpoint n Status Register R/WCY7C67200 CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200Interrupt Enable Device n Interrupt Enable Register R/WCY7C67200 CY7C67200 Page 35 ofDevice n Status Register R/W Device n Address Register WCY7C67200 CY7C67200 Page 37 ofDevice n SOF/EOP Count Register W Device n Frame Number Register RCY7C67200 CY7C67200 OTG Control Register 0xC098 R/WC098H GPIO Control Register 0xC006 R/W CY7C67200GPIO 1 Output Data Register 0xC024 R/W GPIO 0 Output Data Register 0xC01E R/WCY7C67200 GPIO 0 Input Data Register 0xC020 R GPIO 1 Input Data Register 0xC026 RGPIO 0 Direction Register 0xC022 R/W CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WCY7C67200 HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WCY7C67200 HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WCY7C67200 Interrupt Routing Register 0x0142 R HPI Breakpoint Register 0x0140 RCY7C67200 SOF/EOP2 to CPU Enable Bit CY7C67200HPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WCY7C67200 HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200SPI Control Register 0xC0CA R/W CY7C67200Strobe Receive Bit LengthSPI Status Register 0xC0CE R SPI Interrupt Enable Register 0xC0CC R/WCY7C67200 SPI CRC Control Register 0xC0D2 R/W SPI Interrupt Clear Register 0xC0D0 WCY7C67200 SPI Data Register 0xC0D6 R/W SPI CRC Value Register 0xC0D4 R/WCY7C67200 SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WCY7C67200 SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WCY7C67200 UART Status Register 0xC0E2 R UART Control Register 0xC0E0 R/WCY7C67200 UART Data Register 0xC0E4 R/W CY7C67200Pin Descriptions Pin DiagramCY7C67200 CY7C67200 Table 38.Pin Descriptions continuedName TypeAbsolute Maximum Ratings Operating ConditionsCrystal Requirements XTALIN, XTALOUT CY7C67200DC Characteristics CY7C67200AC Timing Characteristics Reset TimingnRESET nRD or nWRL or nWRH CY7C67200Clock Timing 1. I2C EEPROM Bus Timing - Serial I/OXTALIN CY7C67200ADDR nCS nWR nRD Dout CY7C67200tASU tCSSU tCYCADDR CY7C67200CY7C67200 HSS BYTE Mode TransmitHSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceiveHardware CTS/RTS Handshake CY7C67200Page 72 of Register Summary Default HighDefault Low CY7C67200Default High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackPackage Diagram Ordering InformationCY7C67200 Table 43.Ordering InformationDocument History Page “Interrupt Enable Register 0xC00E R/W”CY7C67200 Mode”