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Cypress CY7C67200 manual Registers, CPU Flags Register 0xC000 R

Models: CY7C67200

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Registers

CY7C67200

Registers

Some registers have different functions for a read vs. a write access or USB host vs. USB device mode. Therefore, registers of this type have multiple definitions for the same address.

The default register values listed in this data sheet may be altered to some other value during BIOS initialization. Refer to the BIOS documentation for Register initialization information.

Processor Control Registers

There are eight registers dedicated to general processor control. Each of these registers is covered in this section and is summarized in Table 16.

CPU Flags Register [0xC000] [R]

Table 16.Processor Control Registers

Register Name	Address	R/W
CPU Flags Register	0xC000	R

Register Bank Register	0xC002	R/W

Hardware Revision Register	0xC004	R

CPU Speed Register	0xC008	R/W

Power Control Register	0xC00A	R/W

Interrupt Enable Register	0xC00E	R/W

Breakpoint Register	0xC014	R/W

USB Diagnostic Register	0xC03C	W

Figure 7. CPU Flags Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved...
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4	3	2	1	0
		...Reserved		Global	Negative	Overflow	Carry	Zero
Field				Interrupt	Flag	Flag	Flag	Flag
Field				Enable
Read/Write	-	-	-	R	R	R	R	R
Default	0	0	0	X	X	X	X	X

Register Description

The CPU Flags register is a read only register that gives processor flags status.

Global Interrupt Enable (Bit 4)

The Global Interrupt Enable bit indicates if the Global Inter- rupts are enabled.

1:Enabled

0:Disabled

Negative Flag (Bit 3)

The Negative Flag bit indicates if an arithmetic operation results in a negative answer.

1:MS result bit is ‘1’

0:MS result bit is not ‘1’

Overflow Flag (Bit 2)

The Overflow Flag bit indicates if an overflow condition has occurred. An overflow condition can occur if an arithmetic

result was either larger than the destination operand size (for addition) or smaller than the destination operand should allow for subtraction.

1:Overflow occurred

0:Overflow did not occur

Carry Flag (Bit 1)

The Carry Flag bit indicates if an arithmetic operation resulted in a carry for addition, or borrow for subtraction.

1:Carry/Borrow occurred

0:Carry/Borrow did not occur

Zero Flag (Bit 0)

The Zero Flag bit indicates if an instruction execution resulted in a ‘0’.

1:Zero occurred

0:Zero did not occur

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Registers, CPU Flags Register 0xC000 R

Contents

Typical Applications EZ-OTG FeaturesCY7C67200 CY7C67200Interface Descriptions IntroductionProcessor Core Functional Overview CY7C67200OTG Features USB FeaturesUSB Pins OTG PinsI2C EEPROM Features UART FeaturesUART Pins I2C EEPROM PinsCY7C67200 HPI FeaturesHPI Pins CY7C67200Booster Pins Charge Pump FeaturesCharge Pump Pins CY7C67200Standalone Mode Crystal PinsCoprocessor Mode CY7C67200Figure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings and Reset DescriptionMinimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings Mode DescriptionInternal Memory LCP Variables USB Registers Slave Setup Packet BIOS StackMemory Map 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCPU Flags Register 0xC000 R RegistersCY7C67200 Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WCY7C67200 CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200Pull-down USB Diagnostic Register 0xC03C R/WCY7C67200 Force SelectLock Watchdog Timer Register 0xC00C R/WCY7C67200 StrobeResistors Enable Timer n Register R/WUSB n Control Register R/W CY7C672000xC090/0xC0B0 CY7C67200Pull up/Pull down on D+ and 0xC094/0xC0B4Sequence Host n Control Register R/WCY7C67200 SyncHost n Count Register R/W Host n Address Register R/WCY7C67200 CY7C67200 Host n Endpoint Status Register RLength Host n PID Register W CY7C67200Host n Device Address Register W Host n Count Result Register RCY7C67200 CY7C67200 Host n Interrupt Enable Register R/WPort A Connect CY7C67200 Host n Status Register R/WPort A Connect Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCY7C67200 Device n Endpoint n Control Register R/W Host n Frame Register RCY7C67200 CY7C67200 Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WCY7C67200 Setup Device n Endpoint n Status Register R/WCY7C67200 CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200Interrupt Enable Device n Interrupt Enable Register R/WCY7C67200 CY7C67200 Page 35 ofDevice n Status Register R/W Device n Address Register WCY7C67200 CY7C67200 Page 37 ofDevice n SOF/EOP Count Register W Device n Frame Number Register RCY7C67200 CY7C67200 OTG Control Register 0xC098 R/WC098H GPIO Control Register 0xC006 R/W CY7C67200GPIO 1 Output Data Register 0xC024 R/W GPIO 0 Output Data Register 0xC01E R/WCY7C67200 GPIO 0 Direction Register 0xC022 R/W GPIO 0 Input Data Register 0xC020 RGPIO 1 Input Data Register 0xC026 R CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WCY7C67200 HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WCY7C67200 HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WCY7C67200 Interrupt Routing Register 0x0142 R HPI Breakpoint Register 0x0140 RCY7C67200 SOF/EOP2 to CPU Enable Bit CY7C67200HPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WCY7C67200 HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200Strobe SPI Control Register 0xC0CA R/WCY7C67200 Receive Bit LengthSPI Status Register 0xC0CE R SPI Interrupt Enable Register 0xC0CC R/WCY7C67200 SPI CRC Control Register 0xC0D2 R/W SPI Interrupt Clear Register 0xC0D0 WCY7C67200 SPI Data Register 0xC0D6 R/W SPI CRC Value Register 0xC0D4 R/WCY7C67200 SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WCY7C67200 SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WCY7C67200 UART Status Register 0xC0E2 R UART Control Register 0xC0E0 R/WCY7C67200 UART Data Register 0xC0E4 R/W CY7C67200Pin Descriptions Pin DiagramCY7C67200 Name CY7C67200Table 38.Pin Descriptions continued TypeCrystal Requirements XTALIN, XTALOUT Absolute Maximum RatingsOperating Conditions CY7C67200DC Characteristics CY7C67200nRESET nRD or nWRL or nWRH AC Timing CharacteristicsReset Timing CY7C67200XTALIN Clock Timing1. I2C EEPROM Bus Timing - Serial I/O CY7C67200tASU tCSSU ADDR nCS nWR nRD DoutCY7C67200 tCYCADDR CY7C67200HSS Block Mode Transmit CY7C67200HSS BYTE Mode Transmit HSS BYTE and BLOCK Mode ReceiveHardware CTS/RTS Handshake CY7C67200Page 72 of Default Low Register SummaryDefault High CY7C67200CY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Default HighDefault Low + FeedbackCY7C67200 Package DiagramOrdering Information Table 43.Ordering InformationCY7C67200 Document History Page“Interrupt Enable Register 0xC00E R/W” Mode”