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Cypress CY7C67200 manual HSS Baud Rate Register 0xC072 R/W

Models: CY7C67200

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HSS Baud Rate Register [0xC072] [R/W]

CY7C67200

Transmit Ready (Bit 4)

The Transmit Ready bit is a read only bit that indicates if the HSS Transmit FIFO is ready for the CPU to load new data for transmission.

1:HSS transmit FIFO ready for loading

0:HSS transmit FIFO not ready for loading

Packet Mode Select (Bit 3)

The Packet Mode Select bit selects between Receive Packet Ready and Receive Ready as the interrupt source for the RxIntr interrupt.

1:Selects Receive Packet Ready as the source

0:Selects Receive Ready as the source

Receive Overflow Flag (Bit 2)

The Receive Overflow Flag bit indicates if the Receive FIFO overflowed when set. This flag can be cleared by writing a ‘1’ to this bit.

1:Overflow occurred

0:Overflow did not occur

Receive Packet Ready Flag (Bit 1)

The Receive Packet Ready Flag bit is a read only bit that indicates if the HSS receive FIFO is full with eight bytes.

1:HSS receive FIFO is full

0:HSS receive FIFO is not full

Receive Ready Flag (Bit 0)

The Receive Ready Flag is a read only bit that indicates if the HSS receive FIFO is empty.

1:HSS receive FIFO is not empty (one or more bytes is reading for reading)

0:HSS receive FIFO is empty

HSS Baud Rate Register [0xC072] [R/W]

Figure 49. HSS Baud Rate Register

Bit #	15	14	13	12	11	10	9	8
Field		Reserved				Baud...
Read/Write	-	-	-	R/W	R/W	R/W	R/W	R/W
Default	0	0	0	0	0	0	0	0

Bit #	7	6	5	4		3	2	1	0
Field					...Baud
Read/Write	R/W	R/W	R/W	R/W		R/W	R/W	R/W	R/W
Default	0	0	0	1		0	1	1	1

Register Description

The HSS Baud Rate register sets the HSS Baud Rate. At reset, the default value is 0x0017 which sets the baud rate to 2.0 MHz.

Baud (Bits [12:0])

The Baud field is the baud rate divisor minus one, in units of 1/48 MHz. Therefore the Baud Rate = 48 MHz/(Baud + 1). This puts a constraint on the Baud Value as follows: (24 – 1) < Baud > (5000 – 1)

Reserved

All reserved bits must bit written as ‘0’.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual HSS Baud Rate Register 0xC072 R/W

Contents

CY7C67200 EZ-OTG FeaturesTypical Applications CY7C67200Processor Core Functional Overview IntroductionInterface Descriptions CY7C67200USB Pins USB FeaturesOTG Features OTG PinsUART Pins UART FeaturesI2C EEPROM Features I2C EEPROM PinsHPI Pins HPI FeaturesCY7C67200 CY7C67200Charge Pump Pins Charge Pump FeaturesBooster Pins CY7C67200Coprocessor Mode Crystal PinsStandalone Mode CY7C67200Minimum Hardware Requirements for Standalone Mode - Peripheral Only Power Savings and Reset DescriptionFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionMemory Map LCP Variables USB Registers Slave Setup Packet BIOS StackInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FRegisters CPU Flags Register 0xC000 RCY7C67200 Bank Register 0xC002 R/W Hardware Revision Register 0xC004 RCY7C67200 CY7C67200 CPU Speed Register 0xC008 R/WCY7C67200 Power Control Register 0xC00A R/WCY7C67200 Interrupt Enable Register 0xC00E R/WCY7C67200 Breakpoint Register 0xC014 R/WCY7C67200 USB Diagnostic Register 0xC03C R/WPull-down Force SelectCY7C67200 Watchdog Timer Register 0xC00C R/WLock StrobeUSB n Control Register R/W Timer n Register R/WResistors Enable CY7C67200Pull up/Pull down on D+ and CY7C672000xC090/0xC0B0 0xC094/0xC0B4CY7C67200 Host n Control Register R/WSequence SyncHost n Address Register R/W Host n Count Register R/WCY7C67200 Host n Endpoint Status Register R CY7C67200Length CY7C67200 Host n PID Register WHost n Count Result Register R Host n Device Address Register WCY7C67200 Host n Interrupt Enable Register R/W CY7C67200Port A Connect Host n Status Register R/W CY7C67200Port A Connect Host n SOF/EOP Count Register R/W Host n SOF/EOP Counter Register RCY7C67200 Host n Frame Register R Device n Endpoint n Control Register R/WCY7C67200 CY7C67200 Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/WCY7C67200 Device n Endpoint n Status Register R/W SetupCY7C67200 Page 32 of CY7C67200CY7C67200 Device n Endpoint n Count Result Register R/WDevice n Interrupt Enable Register R/W Interrupt EnableCY7C67200 Page 35 of CY7C67200Device n Address Register W Device n Status Register R/WCY7C67200 Page 37 of CY7C67200Device n Frame Number Register R Device n SOF/EOP Count Register WCY7C67200 OTG Control Register 0xC098 R/W CY7C67200C098H CY7C67200 GPIO Control Register 0xC006 R/WGPIO 0 Output Data Register 0xC01E R/W GPIO 1 Output Data Register 0xC024 R/WCY7C67200 GPIO 1 Input Data Register 0xC026 R GPIO 0 Input Data Register 0xC020 RGPIO 0 Direction Register 0xC022 R/W CY7C67200CY7C67200 GPIO 1 Direction Register 0xC028 R/WCY7C67200 HSS Control Register 0xC070 R/WCY7C67200 HSS Baud Rate Register 0xC072 R/WHSS Transmit Gap Register 0xC074 R/W HSS Data Register 0xC076 R/WCY7C67200 HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/WCY7C67200 HSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WCY7C67200 HPI Breakpoint Register 0x0140 R Interrupt Routing Register 0x0142 RCY7C67200 CY7C67200 SOF/EOP2 to CPU Enable BitSIEXmsg Register W HPI Mailbox Register 0xC0C6 R/WCY7C67200 CY7C67200 HPI Status Port HPI RCY7C67200 SPI Configuration Register 0xC0C8 R/WCY7C67200 3Wire Enable BitCY7C67200 SPI Control Register 0xC0CA R/WStrobe Receive Bit LengthSPI Interrupt Enable Register 0xC0CC R/W SPI Status Register 0xC0CE RCY7C67200 SPI Interrupt Clear Register 0xC0D0 W SPI CRC Control Register 0xC0D2 R/WCY7C67200 SPI CRC Value Register 0xC0D4 R/W SPI Data Register 0xC0D6 R/WCY7C67200 SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/WCY7C67200 SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WCY7C67200 UART Control Register 0xC0E0 R/W UART Status Register 0xC0E2 RCY7C67200 CY7C67200 UART Data Register 0xC0E4 R/WPin Diagram Pin DescriptionsCY7C67200 Table 38.Pin Descriptions continued CY7C67200Name TypeOperating Conditions Absolute Maximum RatingsCrystal Requirements XTALIN, XTALOUT CY7C67200CY7C67200 DC CharacteristicsReset Timing AC Timing CharacteristicsnRESET nRD or nWRL or nWRH CY7C672001. I2C EEPROM Bus Timing - Serial I/O Clock TimingXTALIN CY7C67200CY7C67200 ADDR nCS nWR nRD DouttASU tCSSU tCYCCY7C67200 ADDRHSS BYTE Mode Transmit CY7C67200HSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceiveCY7C67200 Hardware CTS/RTS HandshakePage 72 of Default High Register SummaryDefault Low CY7C67200Default Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackDefault Low Default HighCY7C67200 + FeedbackOrdering Information Package DiagramCY7C67200 Table 43.Ordering Information“Interrupt Enable Register 0xC00E R/W” Document History PageCY7C67200 Mode”