CY7C67200
Device n Interrupt Enable Register [R/W]
•Device 1 Interrupt Enable Register 0xC08C
•Device 2 Interrupt Enable Register 0xC0AC
Figure 35. Device n Interrupt Enable Register
Bit # | 15 | 14 |
| 13 |
| 12 |
| 11 |
| 10 | 9 | 8 |
| VBUS | ID Interrupt |
| Reserved |
| SOF/EOP |
| Reserved | SOF/EOP | Reset | ||
Field | Interrupt | Enable |
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| Timeout |
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| Interrupt | Interrupt |
Enable |
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| Interrupt Enable |
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| Enable | Enable | |
Read/Write | R/W | R/W |
| - |
| - |
| R/W |
| - | R/W | R/W |
Default | 0 | 0 |
| 0 |
| 0 |
| 0 |
| 0 | 0 | 0 |
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Bit # | 7 | 6 |
| 5 |
| 4 |
| 3 | 2 | 1 | 0 | |
Field | EP7 Interrupt | EP6 Interrupt | EP5 Interrupt | EP4 Interrupt | EP3 Interrupt | EP2 Interrupt | EP1 Interrupt | EP0 Interrupt | ||||
Enable | Enable | Enable | Enable | Enable |
| Enable | Enable | Enable | ||||
Read/Write | R/W | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | |||
Default | 0 | 0 |
| 0 |
| 0 |
| 0 | 0 | 0 | 0 | |
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Register Description
The Device n Interrupt Enable register provides control over
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.
1:Enable VBUS interrupt
0:Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Device 1 and is a reserved bit in Device 2.
1:Enable ID interrupt
0:Disable ID interrupt
SOF/EOP Timeout Interrupt Enable (Bit 11)
The SOF/EOP Timeout Interrupt Enable bit enables or disables the SOF/EOP Timeout Interrupt. When enabled this interrupt triggers when the USB host fails to send a SOF or EOP packet within the time period specified in the Device n SOF/EOP Count register. In addition, the Device n Frame register counts the number of times the SOF/EOP Timeout Interrupt triggers between receiving SOF/EOPs.
1:SOF/EOP timeout occurred
0:SOF/EOP timeout did not occur
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP received interrupt.
1:Enable SOF/EOP Received interrupt
0:Disable SOF/EOP Received interrupt
Reset Interrupt Enable (Bit 8)
The Reset Interrupt Enable bit enables or disables the USB Reset Detected interrupt
1:Enable USB Reset Detected interrupt
0:Disable USB Reset Detected interrupt
EP7 Interrupt Enable (Bit 7)
The EP7 Interrupt Enable bit enables or disables an endpoint seven (EP7) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt.
1:Enable EP7 Transaction Done interrupt
0:Disable EP7 Transaction Done interrupt
EP6 Interrupt Enable (Bit 6)
The EP6 Interrupt Enable bit enables or disables an endpoint six (EP6) Transaction Done interrupt. An EPx Transaction Done interrupt triggers when any of the following responses or events occur in a transaction for the device’s given Endpoint: send/receive ACK, send STALL, Timeout occurs, IN Exception Error, or OUT Exception Error. In addition, the NAK Interrupt Enable bit in the Device n Endpoint Control register can also be set so that NAK responses triggers this interrupt.
1:Enable EP6 Transaction Done interrupt
0:Disable EP6 Transaction Done interrupt
Document #: | Page 34 of 78 |
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