Manuals / Cypress / Computer Equipment / Computer Drive

Cypress CY7C67200 manual Pin Descriptions continued, Name, Type

Models: CY7C67200

1 78

Download 78 pages 5 Kb

Page 64

Table 38.Pin Descriptions (continued)

CY7C67200

	Table 38.Pin Descriptions (continued)

	Pin	Name	Type	Description
	H6	GPIO20/A1	IO	GPIO20: General Purpose IO
				A1: HPI A1
	F5	GPIO19/A0	IO	GPIO19: General Purpose IO
				A0: HPI A0
	F6	GPIO15/D15/CTS/	IO	GPIO15: General Purpose IO
		nSSI		D15: D15 for HPI
				CTS: HSS CTS
				nSSI: SPI nSSI
	E4	GPIO14/D14/RTS	IO	GPIO14: General Purpose IO
				D14: D14 for HPI
				RTS: HSS RTS
	E5	GPIO13/D13/RXD	IO	GPIO13: General Purpose IO
				D13: D13 for HPI
				RXD: HSS RXD (Data is received on this pin)
	E6	GPIO12/D12/TXD	IO	GPIO12: General Purpose IO
				D12: D12 for HPI
				TXD: HSS TXD (Data is transmitted from this pin)
	D4	GPIO11/D11/MOSI	IO	GPIO11: General Purpose IO
				D11: D11 for HPI
				MOSI: SPI MOSI
	D5	GPIO10/D10/SCK	IO	GPIO10: General Purpose IO
				D10: D10 for HPI
				SCK: SPI SCK
	C6	GPIO9/D9/nSSI	IO	GPIO9: General Purpose IO
				D9: D9 for HPI
				nSSI: SPI nSSI
	C5	GPIO8/D8/MISO	IO	GPIO8: General Purpose IO
				D8: D8 for HPI
				MISO: SPI MISO
	B5	GPIO7/D7/TX	IO	GPIO7: General Purpose IO
				D7: D7 for HPI
				TX: UART TX (Data is transmitted from this pin)
	B4	GPIO6/D6/RX	IO	GPIO6: General Purpose IO
				D6: D6 for HPI
				RX: UART RX (Data is received on this pin)
	C4	GPIO5/D5	IO	GPIO5: General Purpose IO
				D5: D5 for HPI
	B3	GPIO4/D4	IO	GPIO4: General Purpose IO
				D4: D4 for HPI
	A3	GPIO3/D3	IO	GPIO3: General Purpose IO
				D3: D3 for HPI
	C3	GPIO2/D2	IO	GPIO2: General Purpose IO
				D2: D2 for HPI
	A2	GPIO1/D1	IO	GPIO1: General Purpose IO
				D1: D1 for HPI
	B2	GPIO0/D0	IO	GPIO0: General Purpose IO
				D0: D0 for HPI
	F2	DM1A	IO	USB Port 1A D–
	E3	DP1A	IO	USB Port 1A D+
	C2	DM2A	IO	USB Port 2A D–
	D3	DP2A	IO	USB Port 2A D+
	G3	XTALIN	Input	Crystal Input or Direct Clock Input
	G2	XTALOUT	Output	Crystal output. Leave floating if direct clock source is used.
	A5	nRESET	Input	Reset
Document #: 38-08014 Rev. *G				Page 64 of 78

[+] Feedback

Image 64

Cypress CY7C67200 manual Pin Descriptions continued, Name, Type

Contents

EZ-OTG Features CY7C67200Typical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions CY7C67200USB Features USB PinsOTG Features OTG PinsUART Features UART PinsI2C EEPROM Features I2C EEPROM PinsHPI Features HPI PinsCY7C67200 CY7C67200Charge Pump Features Charge Pump PinsBooster Pins CY7C67200Crystal Pins Coprocessor ModeStandalone Mode CY7C67200Power Savings and Reset Description Minimum Hardware Requirements for Standalone Mode - Peripheral OnlyFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionLCP Variables USB Registers Slave Setup Packet BIOS Stack Memory MapInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCPU Flags Register 0xC000 R RegistersCY7C67200 Hardware Revision Register 0xC004 R Bank Register 0xC002 R/WCY7C67200 CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200USB Diagnostic Register 0xC03C R/W CY7C67200Pull-down Force SelectWatchdog Timer Register 0xC00C R/W CY7C67200Lock StrobeTimer n Register R/W USB n Control Register R/WResistors Enable CY7C67200CY7C67200 Pull up/Pull down on D+ and0xC090/0xC0B0 0xC094/0xC0B4Host n Control Register R/W CY7C67200Sequence SyncHost n Count Register R/W Host n Address Register R/WCY7C67200 CY7C67200 Host n Endpoint Status Register RLength Host n PID Register W CY7C67200Host n Device Address Register W Host n Count Result Register RCY7C67200 CY7C67200 Host n Interrupt Enable Register R/WPort A Connect CY7C67200 Host n Status Register R/WPort A Connect Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCY7C67200 Device n Endpoint n Control Register R/W Host n Frame Register RCY7C67200 CY7C67200 Device n Endpoint n Count Register R/W Device n Endpoint n Address Register R/WCY7C67200 Setup Device n Endpoint n Status Register R/WCY7C67200 CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200Interrupt Enable Device n Interrupt Enable Register R/WCY7C67200 CY7C67200 Page 35 ofDevice n Status Register R/W Device n Address Register WCY7C67200 CY7C67200 Page 37 ofDevice n SOF/EOP Count Register W Device n Frame Number Register RCY7C67200 CY7C67200 OTG Control Register 0xC098 R/WC098H GPIO Control Register 0xC006 R/W CY7C67200GPIO 1 Output Data Register 0xC024 R/W GPIO 0 Output Data Register 0xC01E R/WCY7C67200 GPIO 0 Input Data Register 0xC020 R GPIO 1 Input Data Register 0xC026 RGPIO 0 Direction Register 0xC022 R/W CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WCY7C67200 HSS Receive Counter Register 0xC07A R/W HSS Receive Address Register 0xC078 R/WCY7C67200 HSS Transmit Counter Register 0xC07E R/W HSS Transmit Address Register 0xC07C R/WCY7C67200 Interrupt Routing Register 0x0142 R HPI Breakpoint Register 0x0140 RCY7C67200 SOF/EOP2 to CPU Enable Bit CY7C67200HPI Mailbox Register 0xC0C6 R/W SIEXmsg Register WCY7C67200 HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200SPI Control Register 0xC0CA R/W CY7C67200Strobe Receive Bit LengthSPI Status Register 0xC0CE R SPI Interrupt Enable Register 0xC0CC R/WCY7C67200 SPI CRC Control Register 0xC0D2 R/W SPI Interrupt Clear Register 0xC0D0 WCY7C67200 SPI Data Register 0xC0D6 R/W SPI CRC Value Register 0xC0D4 R/WCY7C67200 SPI Transmit Count Register 0xC0DA R/W SPI Transmit Address Register 0xC0D8 R/WCY7C67200 SPI Receive Count Register 0xC0DE R/W SPI Receive Address Register 0xC0DC R/WCY7C67200 UART Status Register 0xC0E2 R UART Control Register 0xC0E0 R/WCY7C67200 UART Data Register 0xC0E4 R/W CY7C67200Pin Descriptions Pin DiagramCY7C67200 CY7C67200 Table 38.Pin Descriptions continuedName TypeAbsolute Maximum Ratings Operating ConditionsCrystal Requirements XTALIN, XTALOUT CY7C67200DC Characteristics CY7C67200AC Timing Characteristics Reset TimingnRESET nRD or nWRL or nWRH CY7C67200Clock Timing 1. I2C EEPROM Bus Timing - Serial I/OXTALIN CY7C67200ADDR nCS nWR nRD Dout CY7C67200tASU tCSSU tCYCADDR CY7C67200CY7C67200 HSS BYTE Mode TransmitHSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceiveHardware CTS/RTS Handshake CY7C67200Page 72 of Register Summary Default HighDefault Low CY7C67200Default High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackPackage Diagram Ordering InformationCY7C67200 Table 43.Ordering InformationDocument History Page “Interrupt Enable Register 0xC00E R/W”CY7C67200 Mode”