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Cypress CY7C67200 manual Host n Control Register R/W, Sequence, Sync

Models: CY7C67200

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Host n Control Register [R/W]

CY7C67200

Host n Control Register [R/W]

•Host 1 Control Register 0xC080

•Host 2 Control Register 0xC0A0

Figure 18. Host n Control Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	Preamble	Sequence	Sync	ISO		Reserved		Arm
Field	Enable	Select	Enable	Enable				Enable
Read/Write	R/W	R/W	R/W	R/W	-	-	-	R/W
Default	0	0	0	0	0	0	0	0

Register Description

The Host n Control register allows high-level USB transaction control.

Preamble Enable (Bit 7)

The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should only be set when communicating with a low-speed device.

1:Enable Preamble packet

0:Disable Preamble packet

Sequence Select (Bit 6)

The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.

1:Send DATA1

0:Send DATA0

Sync Enable (Bit 5)

The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.

1:The next enabled packet will be transferred after the SOF or EOP packet is transmitted

0:The next enabled packet will be transferred as soon as the SIE is free

ISO Enable (Bit 4)

The ISO Enable bit enables or disables an Isochronous trans- action.

1:Enable Isochronous transaction

0:Disable Isochronous transaction

Arm Enable (Bit 0)

The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is complete.

1:Arm endpoint and begin transaction

0:Endpoint disarmed

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Host n Control Register R/W, Sequence, Sync

Contents

EZ-OTG Features CY7C67200Typical Applications CY7C67200Introduction Processor Core Functional OverviewInterface Descriptions CY7C67200USB Features USB PinsOTG Features OTG PinsUART Features UART PinsI2C EEPROM Features I2C EEPROM PinsHPI Features HPI PinsCY7C67200 CY7C67200Charge Pump Features Charge Pump PinsBooster Pins CY7C67200Crystal Pins Coprocessor ModeStandalone Mode CY7C67200Power Savings and Reset Description Minimum Hardware Requirements for Standalone Mode - Peripheral OnlyFigure 5. Minimum Standalone Hardware Configuration - Peripheral Only Power Savings Mode DescriptionLCP Variables USB Registers Slave Setup Packet BIOS Stack Memory MapInternal Memory 0x0000 - 0x00FF 0x0100 - 0x011F 0x0120 - 0x013FCY7C67200 RegistersCPU Flags Register 0xC000 R CY7C67200 Bank Register 0xC002 R/WHardware Revision Register 0xC004 R CPU Speed Register 0xC008 R/W CY7C67200Power Control Register 0xC00A R/W CY7C67200Interrupt Enable Register 0xC00E R/W CY7C67200Breakpoint Register 0xC014 R/W CY7C67200USB Diagnostic Register 0xC03C R/W CY7C67200Pull-down Force SelectWatchdog Timer Register 0xC00C R/W CY7C67200Lock StrobeTimer n Register R/W USB n Control Register R/WResistors Enable CY7C67200CY7C67200 Pull up/Pull down on D+ and0xC090/0xC0B0 0xC094/0xC0B4Host n Control Register R/W CY7C67200Sequence SyncCY7C67200 Host n Address Register R/WHost n Count Register R/W Length Host n Endpoint Status Register RCY7C67200 Host n PID Register W CY7C67200CY7C67200 Host n Count Result Register RHost n Device Address Register W Port A Connect Host n Interrupt Enable Register R/WCY7C67200 Port A Connect Host n Status Register R/WCY7C67200 CY7C67200 Host n SOF/EOP Count Register R/WHost n SOF/EOP Counter Register R CY7C67200 Host n Frame Register RDevice n Endpoint n Control Register R/W CY7C67200 CY7C67200 Device n Endpoint n Address Register R/WDevice n Endpoint n Count Register R/W CY7C67200 Device n Endpoint n Status Register R/WSetup CY7C67200 Page 32 ofDevice n Endpoint n Count Result Register R/W CY7C67200CY7C67200 Device n Interrupt Enable Register R/WInterrupt Enable CY7C67200 Page 35 ofCY7C67200 Device n Address Register WDevice n Status Register R/W CY7C67200 Page 37 ofCY7C67200 Device n Frame Number Register RDevice n SOF/EOP Count Register W C098H OTG Control Register 0xC098 R/WCY7C67200 GPIO Control Register 0xC006 R/W CY7C67200CY7C67200 GPIO 0 Output Data Register 0xC01E R/WGPIO 1 Output Data Register 0xC024 R/W GPIO 0 Input Data Register 0xC020 R GPIO 1 Input Data Register 0xC026 RGPIO 0 Direction Register 0xC022 R/W CY7C67200GPIO 1 Direction Register 0xC028 R/W CY7C67200HSS Control Register 0xC070 R/W CY7C67200HSS Baud Rate Register 0xC072 R/W CY7C67200CY7C67200 HSS Transmit Gap Register 0xC074 R/WHSS Data Register 0xC076 R/W CY7C67200 HSS Receive Address Register 0xC078 R/WHSS Receive Counter Register 0xC07A R/W CY7C67200 HSS Transmit Address Register 0xC07C R/WHSS Transmit Counter Register 0xC07E R/W CY7C67200 HPI Breakpoint Register 0x0140 RInterrupt Routing Register 0x0142 R SOF/EOP2 to CPU Enable Bit CY7C67200CY7C67200 SIEXmsg Register WHPI Mailbox Register 0xC0C6 R/W HPI Status Port HPI R CY7C67200SPI Configuration Register 0xC0C8 R/W CY7C672003Wire Enable Bit CY7C67200SPI Control Register 0xC0CA R/W CY7C67200Strobe Receive Bit LengthCY7C67200 SPI Interrupt Enable Register 0xC0CC R/WSPI Status Register 0xC0CE R CY7C67200 SPI Interrupt Clear Register 0xC0D0 WSPI CRC Control Register 0xC0D2 R/W CY7C67200 SPI CRC Value Register 0xC0D4 R/WSPI Data Register 0xC0D6 R/W CY7C67200 SPI Transmit Address Register 0xC0D8 R/WSPI Transmit Count Register 0xC0DA R/W CY7C67200 SPI Receive Address Register 0xC0DC R/WSPI Receive Count Register 0xC0DE R/W CY7C67200 UART Control Register 0xC0E0 R/WUART Status Register 0xC0E2 R UART Data Register 0xC0E4 R/W CY7C67200CY7C67200 Pin DiagramPin Descriptions CY7C67200 Table 38.Pin Descriptions continuedName TypeAbsolute Maximum Ratings Operating ConditionsCrystal Requirements XTALIN, XTALOUT CY7C67200DC Characteristics CY7C67200AC Timing Characteristics Reset TimingnRESET nRD or nWRL or nWRH CY7C67200Clock Timing 1. I2C EEPROM Bus Timing - Serial I/OXTALIN CY7C67200ADDR nCS nWR nRD Dout CY7C67200tASU tCSSU tCYCADDR CY7C67200CY7C67200 HSS BYTE Mode TransmitHSS Block Mode Transmit HSS BYTE and BLOCK Mode ReceivePage 72 of CY7C67200Hardware CTS/RTS Handshake Register Summary Default HighDefault Low CY7C67200Default High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackDefault High Default LowCY7C67200 + FeedbackPackage Diagram Ordering InformationCY7C67200 Table 43.Ordering InformationDocument History Page “Interrupt Enable Register 0xC00E R/W”CY7C67200 Mode”