Preamble Enable Bit, Sequence Select Bit | Cypress CY7C67200

CY7C67200

Host n Control Register [R/W]

•Host 1 Control Register 0xC080

•Host 2 Control Register 0xC0A0

Figure 18. Host n Control Register

Bit #	15	14	13	12		11	10	9	8
Field					Reserved
Read/Write	-	-	-	-		-	-	-	-
Default	0	0	0	0		0	0	0	0

Bit #	7	6	5	4	3	2	1	0
Field	Preamble	Sequence	Sync	ISO		Reserved		Arm
Field	Enable	Select	Enable	Enable				Enable
Read/Write	R/W	R/W	R/W	R/W	-	-	-	R/W
Default	0	0	0	0	0	0	0	0

Register Description

The Host n Control register allows high-level USB transaction control.

Preamble Enable (Bit 7)

The Preamble Enable bit enables or disables the transmission of a preamble packet before all low-speed packets. This bit should only be set when communicating with a low-speed device.

1:Enable Preamble packet

0:Disable Preamble packet

Sequence Select (Bit 6)

The Sequence Select bit sets the data toggle for the next packet. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.

1:Send DATA1

0:Send DATA0

Sync Enable (Bit 5)

The Sync Enable bit synchronizes the transfer with the SOF packet in full-speed mode and the EOP packet in low-speed mode.

1:The next enabled packet will be transferred after the SOF or EOP packet is transmitted

0:The next enabled packet will be transferred as soon as the SIE is free

ISO Enable (Bit 4)

The ISO Enable bit enables or disables an Isochronous trans- action.

1:Enable Isochronous transaction

0:Disable Isochronous transaction

Arm Enable (Bit 0)

The Arm Enable bit arms an endpoint and starts a transaction. This bit is automatically cleared to ‘0’ when a transaction is complete.

1:Arm endpoint and begin transaction

0:Endpoint disarmed

Reserved

All reserved bits must be written as ‘0’.

Document #: 38-08014 Rev. *G

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Cypress CY7C67200 manual Preamble Enable Bit, Sequence Select Bit, Sync Enable Bit, ISO Enable Bit, Arm Enable Bit

Contents

EZ-OTG Features Typical ApplicationsCY7C67200 CY16 Interface Descriptions IntroductionProcessor Core Functional Overview USB Interface Pins Pin Name Pin Number OTG Interface Pins Pin Name Pin NumberUSB Interface OTG Interface I2C Eeprom Interface Pins Pin Name Pin Number SPI Interface Pins Pin Name Pin NumberHSS Interface Pins Pin Name Pin Number Serial Peripheral Interface HPI Interface Pins 1 Pin Name Pin Number Host Port Interface HPIHPI Addressing HPI A10 Charge Pump Interface Crystal Interface Charge Pump Interface Pins Pin Name Pin NumberBooster Interface Crystal Pins Pin Name Pin Number Boot Configuration InterfaceBoot Mode Pin Sleep Power Savings and Reset DescriptionPower Savings Mode Description Memory Map Registers Bank Register 0xC002 R/W Bank Register Example Hex Value Binary ValueReserved Hardware Revision Register 0xC004 R CPU Speed Register 0xC008 R/W CPU Speed Definition Processor Speed Host/Device 2 Wake Enable Bit Host/Device 1 Wake Enable BitOTG Wake Enable Bit HSS Wake Enable Bit Halt Enable Bit OTG Interrupt Enable BitSPI Interrupt Enable Bit Host/Device 2 Interrupt Enable Bit Uart Interrupt Enable Bit Gpio Interrupt Enable BitTimer 1 Interrupt Enable Bit Timer 0 Interrupt Enable Bit Port 2A Diagnostic Enable Bit Port 1A Diagnostic Enable BitPull-down Enable Bit LS Pull-up Enable Bit Timeout Flag Bit Lock Enable BitWDT Enable Bit Reset Strobe Bit Timer n Register R/W General USB RegistersUSB Registers Register Name Address SIE1/SIE2 0xC08A/0xC0AA Mode Select Bit Port a Resistors Enable BitUSB Data Line Pull-up and Pull-down Resistors Mode Port n Resistors Function Select Enable Preamble Enable Bit Sync Enable BitISO Enable Bit Arm Enable Bit Host 1 Count Register 0xC084 Host 2 Count Register 0xC0A4 Host n Address Register R/WHost n Count Register R/W Error Flag Bit Underflow Flag BitStall Flag Bit NAK Flag Bit ACK Flag Bit Host n PID Register WPID Select Definition PID Select Host n Count Result Register R Host n Device Address Register W Vbus Interrupt Enable Bit ID Interrupt Enable BitSOF/EOP Interrupt Enable Bit Port a Wake Interrupt Enable Bit Vbus Interrupt Flag Bit ID Interrupt Flag BitSOF/EOP Interrupt Flag Bit Port a Wake Interrupt Flag Bit Host n SOF/EOP Counter Register R Host n SOF/EOP Count Register R/WCount Bits Count field sets the SOF/EOP counter duration Host n Frame Register R USB Device Only Registers ReservedUSB Device Only Registers Register Name Address Device 1/Device IN/OUT Ignore Enable Bit Stall Enable BitNAK Interrupt Enable Bit Enable Bit Device n Endpoint n Address Register R/W Device n Endpoint n Count Register R/W Device n Endpoint n Status Register R/W OUT Exception Flag Bit Setup Flag Bit Timeout occurred Timeout condition did not occurError occurred Error did not occur Exception Flag Bit Device n Endpoint n Count Result Register R/W Device n Endpoint n Count Result Register Device n Interrupt Enable Register R/W SOF/EOP Timeout Interrupt Enable BitReset Interrupt Enable Bit EP7 Interrupt Enable Bit EP5 Interrupt Enable Bit EP2 Interrupt Enable Bit EP4 Interrupt Enable BitEP3 Interrupt Enable Bit EP1 Interrupt Enable Bit Device n Address Register W Device n Status Register R/W Reset Interrupt Flag Bit EP7 Interrupt Flag BitEP6 Interrupt Flag Bit EP5 Interrupt Flag Bit SOF/EOP Timeout Flag Bit SOF/EOP Timeout Interrupt Counter BitsDevice n Frame Number Register R Device n SOF/EOP Count Register W Vbus Pull-up Enable Bit Receive Disable BitCharge Pump Enable Bit Vbus Discharge Enable Bit Write Protect Enable Bit SAS Enable BitMode Select Definition Gpio Configuration 108 111 Reserved Vbus Valid Flag Bit HSS Enable Bit SPI Enable BitInterrupt 0 Enable Bit Interrupt 0 Polarity Select Bit Gpio 0 Direction Register 0xC022 R/W Gpio 0 Input Data Register 0xC020 RGpio 1 Input Data Register 0xC026 R HSS Registers Register Name Address Gpio 1 Direction Register 0xC028 R/WHSS Registers Xoff Enable Bit CTS Enable BitReceive Interrupt Enable Bit RTS Polarity Select Bit Packet Mode Select Bit Transmit Ready BitReceive Overflow Flag Bit Receive Packet Ready Flag Bit HSS Data Register 0xC076 R/W HSS Transmit Gap Register 0xC074 R/WTransmit Gap Select Bits HSS Receive Address Register 0xC078 R/W HSS Receive Counter Register 0xC07A R/W HSS Transmit Address Register 0xC07C R/W HSS Transmit Counter Register 0xC07E R/WHPI Registers HPI Registers Register Name Address Vbus to HPI Enable Bit ID to HPI Enable BitSOF/EOP2 to HPI Enable Bit HPI Breakpoint Register 0x0140 R SOF/EOP2 to CPU Enable Bit SOF/EOP1 to HPI Enable BitSOF/EOP1 to CPU Enable Bit Reset2 to HPI Enable Bit SIEXmsg Register W SIE1msg Register SIE2msg RegisterData Bits HPI Mailbox Register 0xC0C6 R/W Reset2 Flag Bit Vbus Flag BitID Flag Bit SOF/EOP2 Flag Bit SPI Registers Reset1 Flag Bit Done1 Flag BitMailbox Out Flag Bit SPI Registers Register Name Address 3Wire Enable Bit Phase Select BitMaster Active Enable Bit Master Enable Bit Byte Mode Bit Read Enable BitSCK Strobe Bit Fifo Init Bit Transmit Interrupt Enable Bit Transfer Interrupt Enable BitFifo Error Flag Bit Receive Bit Length Bits CRC Mode Definition CRCMode CRC Polynomial Transmit Interrupt Flag BitTransfer Interrupt Flag Bit Transmit Interrupt Clear Bit CRC Enable Bit CRC Clear BitReceive CRC Bit One in CRC Bit SPI Transmit Address Register 0xC0D8 R/W SPI Transmit Count Register 0xC0DA R/W SPI Receive Address Register 0xC0DC R/W SPI Receive Count Register 0xC0DE R/WUart Registers Uart Registers Register Name Address Uart Enable Bit Scale Select BitBaud Select Bits Uart Baud Select Definition Baud Rate DIV8 = Transmit Full Bit Uart Data Register 0xC0E4 R/W Pin Descriptions Name Type Pin DiagramPin Descriptions GPIO20 General Purpose IO A1 HPI A1GPIO19 General Purpose IO A0 HPI A0 Booster Power Input 2.7V to Absolute Maximum RatingsOperating Conditions Crystal Requirements XTALIN, Xtalout DC Characteristics AC Timing Characteristics Reset Timing Parameter Description Min Typical Max Unit Clock TimingI2C Eeprom Timing HPI Host Port Interface Write Cycle Timing Data Access Time, from HPInRD falling HPI Host Port Interface Read Cycle TimingRead Pulse Width Read Cycle Time Document # 38-08014 Rev. *G HSS Byte and Block Mode Receive HSS Byte Mode TransmitHSS Block Mode Transmit Hardware CTS/RTS Handshake Hssrts Hsscts Register Summary Register Summary GPIO31 GPIO30 GPIO29 SE0 SOF/EOP2 Package Diagram Ordering InformationOrdering Information Ordering Code Package Type PB-Free Ball 7.00 mm x 7.00 mm x 1.2 mm Fbga BA48 Issue Orig. Description of Change Date Document History