CY7C67300
Hardware CTS/RTS Handshake
tCTShold
tCTSsetup
HSS_RTS
HSS_CTS
HSS_TxD 
Start of transmission delayed until HSS_CTS goes high
tCTShold |
tCTSsetup |
Start of transmission not delayed by HSS_CTS
tCTSsetup: HSS_CTS setup time before HSS_RTS = 1.5T min.
tCTShold: HSS_CTS hold time after START bit = 0 ns min. T = 1/48 MHz.
When RTS/CTS hardware handshake is enabled, transmission can be help off by deasserting HSS_CTS at least 1.5T before HSS_RTS. Transmission resumes when HSS_CTS returns HIGH. HSS_CTS must remain HIGH until START bit.
HSS_RTS is deasserted in the third data bit time.
An application may choose to hold HSS_CTS until HSS_RTS is deasserted, which always occurs after the START bit.
Register Summary
Table 142. | Register Summary |
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R/W | Address | Register | Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit 9 | Bit 8 | Default High |
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| Bit 7 | Bit 6 | Bit 5 | Bit 4 | Bit 3 | Bit 2 | Bit 1 | Bit 0 | Default Low |
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R | 0x0140 | HPI Breakpoint | Address... |
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| 0000 0000 |
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| ...Address |
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| 0000 0000 |
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R | 0x0142 | Interrupt Routing | VBUS to HPI | ID to HPI | SOF/EOP2 to | SOF/EOP2 to | SOF/EOP1 to | SOF/EOP1 to | Reset2 to HPI | HPI Swap 1 | 0001 0100 |
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| Enable | Enable | HPI Enable | CPU Enable | HPI Enable | CPU Enable | Enable | Enable |
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| Resume2 to | Resume1 to | Reserved |
| Done2 to HPI | Done1 to HPI | Reset1 to HPI | HPI Swap 0 | 0000 0000 |
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| HPI Enable | HPI Enable |
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| Enable | Enable | Enable | Enable |
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W | 1: 0x0144 | SIEXmsg | Data... |
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| xxxx xxxx |
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| 2: 0x0148 |
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| ...Data |
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| xxxx xxxx |
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R/W | 0x02n0 | Device n Endpoint n Control | Reserved |
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| xxxx xxxx |
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| IN/OUT | Sequence | Stall | ISO | NAK Interrupt | Direction | Enable | ARM | xxxx xxxx |
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| Ignore Enable | Select | Enable | Enable | Enable | Select |
| Enable |
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R/W | 0x02n2 | Device n Endpoint n Address | Address... |
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| xxxx xxxx |
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| ...Address |
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| xxxx xxxx |
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R.W | 0x02n4 | Device n Endpoint n Count | Reserved |
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| Count... |
| xxxx xxxx |
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| ...Count |
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| xxxx xxxx |
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R/W | 0x02n6 | Device n Endpoint n Status | Reserved |
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| Overflow | Underflow | OUT | IN | xxxx xxxx |
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| Flag | Flag | Exception Flag | Exception Flag |
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| Stall | NAK | Length | Setup | Sequence | Timeout | Error | ACK | xxxx xxxx |
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| Flag | Flag | Exception Flag | Flag | Status | Flag | Flag | Flag |
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R/W | 0x02n8 | Device n Endpoint n Count Result | Result... |
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| xxxx xxxx |
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| ...Result |
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| xxxx xxxx |
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R | 0xC000 | CPU Flags | Reserved... |
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| 0000 0000 |
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| ...Reserved |
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| Global Inter- | Negative | Overflow | Carry | Zero | 000x xxxx |
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| rupt Enable | Flag | Flag | Flag | Flag |
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R/W | 0xC002 | Bank | Address... |
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| 0000 0001 |
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| ...Address |
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| Reserved |
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| 000x xxxx |
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R | 0xC004 | Hardware Revision | Revision... |
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| xxxx xxxx |
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| ...Revision |
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| xxxx xxxx |
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R/W | 0xC006 | GPIO Control | Write Protect | UD | Reserved |
| SAS | Mode |
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| 0000 0000 |
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| Enable |
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| Enable | Select |
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| HSS | HSS XD | SPI | SPI XD | Interrupt 1 | Interrupt 1 | Interrupt 0 | Interrupt 0 | 0000 0000 |
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| Enable | Enable | Enable | Enable | Polarity | Enable | Polarity | Enable |
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| Select |
| Select |
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R/W | 0xC008 | CPU Speed | Reserved... |
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| 0000 0000 |
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| .Reserved |
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| CPU Speed |
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| 0000 1111 |
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R/W | 0xC00A | Power Control | Host/Device | Host/Device | Host/Device | Host/Device | OTG | Reserved | HSS | SPI | 0000 0000 |
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| 2B Wake | 2A Wake | 1B Wake | 1A Wake | Wake |
| Wake | Wake |
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| Enable | Enable | Enable | Enable | Enable |
| Enable | Enable |
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| HPI | Reserved |
| GPI | Reserved | Boost 3V | Sleep | Halt | 0000 0000 |
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| Wake Enable |
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| Wake Enable |
| OK | Enable | Enable |
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Document #: |
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| Page 92 of 99 | |||
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