![](/images/new-backgrounds/1192266/192266143x1.webp)
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| CY7C67300 | |||
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SPI Transmit Count Register [0xC0DA] [R/W] |
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Table 116. SPI Transmit Count Register |
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Bit # | 15 |
| 14 |
| 13 | 12 |
| 11 | 10 | 9 |
| 8 |
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Field |
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| Reserved |
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| Count... |
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Read/Write | - |
| - |
| - | - |
| - | R/W | R/W |
| R/W |
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Default | 0 |
| 0 |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Bit # | 7 |
| 6 |
| 5 | 4 |
| 3 | 2 | 1 |
| 0 |
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Field |
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| ...Count |
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Read/Write | R/W |
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| R/W |
| R/W | R/W |
| R/W | R/W | R/W |
| R/W |
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Default | 0 |
| 0 |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Register Description |
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| Reserved |
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The SPI Transmit Count register designates the block byte | Write all reserved bits with ’0’. |
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length for the SPI transmit DMA transfer. |
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Count (Bits [10:0])
The Count field sets the count for the SPI transmit DMA transfer.
SPI Receive Address Register [0xC0DC [R/W]
Table 117. SPI Receive Address Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
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| Address... |
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Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Field |
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| ...Address |
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Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Register Description
The SPI Receive Address register is issued as the base address for the SPI Receive DMA.
SPI Receive Count Register [0xC0DE] [R/W]
Table 118. SPI Receive Count Register
Address (Bits [15:0])
The Address field sets the base address for the SPI receive DMA.
Bit # | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
Field |
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| Reserved |
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| Count... |
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Read/Write | - | - | - | - | - | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Field |
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| ...Count |
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Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Document #: | Page 72 of 99 |
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