CY7C67300

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HSS Receive Address Register [0xC078] [R/W]

 

 

 

 

 

 

 

 

 

 

Table 94. HSS Receive Address Register

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

15

14

 

13

12

 

11

10

9

 

8

 

 

Field

 

 

 

 

 

 

 

Address...

 

 

 

 

 

 

Read/Write

R/W

 

 

R/W

 

R/W

R/W

 

R/W

R/W

R/W

 

R/W

 

 

Default

0

0

 

0

0

 

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

 

5

4

 

3

2

1

 

0

 

 

Field

 

 

 

 

 

 

 

...Address

 

 

 

 

 

 

Read/Write

R/W

 

 

R/W

 

R/W

R/W

 

R/W

R/W

R/W

 

R/W

 

 

Default

0

0

 

0

0

 

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Register Description

The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.

HSS Receive Counter Register [0xC07A] [R/W]

Table 95. HSS Receive Counter Register

Address (Bits [15:0])

The Address field sets the base pointer address for the next HSS block receive transfer.

Bit #

15

14

13

 

12

11

10

9

 

8

Field

 

 

 

Reserved

 

 

 

Counter...

Read/Write

-

-

-

 

-

-

-

R/W

 

R/W

Default

0

0

0

 

0

0

0

0

 

0

 

 

 

 

 

 

 

 

 

 

 

Bit #

7

6

5

4

 

3

2

1

0

Field

 

 

 

 

...Counter

 

 

 

Read/Write

R/W

R/W

R/W

R/W

 

R/W

R/W

R/W

R/W

Default

0

0

0

0

 

0

0

0

0

 

 

 

 

 

 

 

 

 

 

Register Description

The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. Load this register with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer.

Counter (Bits [9:0])

The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded.

Reserved

Write all reserved bits with ’0’.

Document #: 38-08015 Rev. *J

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Cypress CY7C67300 manual HSS Receive Counter Register 0xC07A R/W