![](/images/new-backgrounds/1192266/192266117x1.webp)
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HSS Receive Address Register [0xC078] [R/W] |
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Table 94. HSS Receive Address Register |
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Bit # | 15 | 14 |
| 13 | 12 |
| 11 | 10 | 9 |
| 8 |
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Field |
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| Address... |
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Read/Write | R/W |
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| R/W |
| R/W | R/W |
| R/W | R/W | R/W |
| R/W |
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Default | 0 | 0 |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Bit # | 7 | 6 |
| 5 | 4 |
| 3 | 2 | 1 |
| 0 |
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Field |
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| ...Address |
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Read/Write | R/W |
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| R/W |
| R/W | R/W |
| R/W | R/W | R/W |
| R/W |
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Default | 0 | 0 |
| 0 | 0 |
| 0 | 0 | 0 |
| 0 |
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Register Description
The HSS Receive Address register is used as the base pointer address for the next HSS block receive transfer.
HSS Receive Counter Register [0xC07A] [R/W]
Table 95. HSS Receive Counter Register
Address (Bits [15:0])
The Address field sets the base pointer address for the next HSS block receive transfer.
Bit # | 15 | 14 | 13 |
| 12 | 11 | 10 | 9 |
| 8 |
Field |
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| Reserved |
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| Counter... | ||
Read/Write | - | - | - |
| - | - | - | R/W |
| R/W |
Default | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
| 0 |
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Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Field |
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| ...Counter |
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Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Register Description
The HSS Receive Counter register designates the block byte length for the next HSS receive transfer. Load this register with the word count minus one to start the block receive transfer. As each byte is received this register value is decremented. When read, this register indicates the remaining length of the transfer.
Counter (Bits [9:0])
The Counter field value is equal to the word count minus one giving a maximum value of 0x03FF (1023) or 2048 bytes. When the transfer is complete this register returns 0x03FF until reloaded.
Reserved
Write all reserved bits with ’0’.
Document #: | Page 59 of 99 |
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