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CY7C67300
IDE PIO Port Registers [0xC050 - 0xC06F] [R/W]
All IDE PIO Port registers [0xC050 - 0xC06F] in Table 88 are defined in detail in the Information
Table 88. IDE PIO Port Registers
Address | ATA/ATAPI Register | IDE_nCS[1:0] | IDE_A[2:0] |
0xC050 | DATA Register | ‘10’ | ‘000’ |
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0xC052 | Read: Error Register | ‘10’ | ‘001’ |
| Write: Feature Register |
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0xC054 | Sector Count Register | ‘10’ | ‘010’ |
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0xC056 | Sector Number Register | ‘10’ | ‘011’ |
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0xC058 | Cylinder Low Register | ‘10’ | ‘100’ |
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0xC05A | Cylinder High Register | ‘10’ | ‘101’ |
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0xC05C | Device/Head Register | ‘10’ | ‘110’ |
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0xC05E | Read: Status Register | ‘10’ | ‘111’ |
| Write: Command Register |
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0xC060 | Not Defined | ‘01’ | ‘000’ |
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0xC062 | Not Defined | ‘01’ | ‘001’ |
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0xC064 | Not Defined | ‘01’ | ‘010’ |
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0xC066 | Not Defined | ‘01’ | ‘011’ |
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0xC068 | Not Defined | ‘01’ | ‘100’ |
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0xC06A | Not Defined | ‘01’ | ‘101’ |
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0xC06C | Read: Alternate Status Register | ‘01’ | ‘110’ |
| Write: Device Control Register |
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0xC06E | Not Defined | ‘01’ | ‘111’ |
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HSS Registers
There are eight registers dedicated to HSS operation. Each of these registers are covered in this section and summarized in Table 89.
Table 89. HSS Registers
Register Name | Address | R/W |
HSS Control Register | 0xC070 | R/W |
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HSS Baud Rate Register | 0xC072 | R/W |
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HSS Transmit Gap Register | 0xC074 | R/W |
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HSS Data Register | 0xC076 | R/W |
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HSS Receive Address Register | 0xC078 | R/W |
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HSS Receive Length Register | 0xC07A | R/W |
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HSS Transmit Address Register | 0xC07C | R/W |
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HSS Transmit Length Register | 0xC07E | R/W |
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Document #: | Page 55 of 99 |
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