Cypress CY7C67300 ID to HPI Enable Bit, SOF/EOP2 to HPI Enable Bit, SOF/EOP2 to CPU Enable Bit

CY7C67300

ID to HPI Enable (Bit 14)

The ID to HPI Enable bit routes the OTG ID interrupt to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

SOF/EOP2 to HPI Enable (Bit 13)

The SOF/EOP2 to HPI Enable bit routes the SOF/EOP2 interrupt to the HPI port.

1:Route signal to HPI port

0: Do not route signal to HPI port

SOF/EOP2 to CPU Enable (Bit 12)

The SOF/EOP2 to CPU Enable bit routes the SOF/EOP2 interrupt to the on-chip CPU. Since the SOF/EOP2 interrupt can be routed to both the on-chip CPU and the HPI port, the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.

1:Route signal to CPU

0:Do not route signal to CPU

SOF/EOP1 to HPI Enable (Bit 11)

The SOF/EOP1 to HPI Enable bit routes the SOF/EOP1 interrupt to the HPI port.

1:Route signal to HPI port

0:Do not route signal to HPI port

SOF/EOP1 to CPU Enable (Bit 10)

The SOF/EOP1 to CPU Enable bit routes the SOF/EOP1 interrupt to the on-chip CPU. Since the SOF/EOP1 interrupt can be routed to both the on-chip CPU and the HPI port, the firmware must ensure only one of the two (CPU, HPI) resets the interrupt.

1:Route signal to CPU

0:Do not route signal to CPU

Reset2 to HPI Enable (Bit 9)

The Reset2 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 2 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

HPI Swap 1 Enable (Bit 8)

Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].

Resume2 to HPI Enable (Bit 7)

The Resume2 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 2 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

Resume1 to HPI Enable (Bit 6)

The Resume1 to HPI Enable bit routes the USB Resume interrupt that occurs on Host 1 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

Done2 to HPI Enable (Bit 3)

The Done2 to HPI Enable bit routes the Done interrupt for Host/Device 2 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

Done1 to HPI Enable (Bit 2)

The Done1 to HPI Enable bit routes the Done interrupt for Host/Device 1 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

Reset1 to HPI Enable (Bit 1)

The Reset1 to HPI Enable bit routes the USB Reset interrupt that occurs on Device 1 to the HPI port instead of the on-chip CPU.

1:Route signal to HPI port

0:Do not route signal to HPI port

HPI Swap 0 Enable (Bit 0)

Both HPI Swap bits (bits 8 and 0) must be set to identical values. When set to ‘00’, the most significant data byte goes to HPI_D[15:8] and the least significant byte goes to HPI_D[7:0]. This is the default setting. By setting to ‘11’, the most significant data byte goes to HPI_D[7:0] and the least significant byte goes to HPI_D[15:8].

Document #: 38-08015 Rev. *J Page 62 of 99

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