CY7C67300
SOF/EOP Interrupt Enable (Bit 9)
The SOF/EOP Interrupt Enable bit enables or disables the SOF/EOP timer interrupt
1:Enable SOF/EOP timer interrupt
0:Disable SOF/EOP timer interrupt
Port B Wake Interrupt Enable (Bit 7)
The Port B Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port B
1:Enable remote wakeup interrupt for Port B
0:Disable remote wakeup interrupt for Port B
Port A Wake Interrupt Enable (Bit 6)
The Port A Wake Interrupt Enable bit enables or disables the remote wakeup interrupt for Port A
1:Enable remote wakeup interrupt for Port A
0:Disable remote wakeup interrupt for Port A
Port B Connect Change Interrupt Enable (Bit 5)
The Port B Connect Change Interrupt Enable bit enables or disables the Port B Connect Change interrupt on Port B. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
Host n Status Register [R/W]
■Host 1 Status Register 0xC090
■Host 2 Status Register 0xC0B0
Table 58. Host n Status Register
1:Enable Connect Change interrupt
0:Disable Connect Change interrupt
Port A Connect Change Interrupt Enable (Bit 4)
The Port A Connect Change Interrupt Enable bit enables or disables the Connect Change interrupt on Port A. This interrupt triggers when either a device is inserted (SE0 state to J state) or a device is removed (J state to SE0 state).
1:Enable Connect Change interrupt
0:Disable Connect Change interrupt
Done Interrupt Enable (Bit 0)
The Done Interrupt Enable bit enables or disables the USB Transfer Done interrupt. The USB Transfer Done triggers when either the host responds with an ACK, or a device responds with any of the following: ACK, NAK, STALL, or Timeout. This interrupt is used for both Port A and Port B.
1:Enable USB Transfer Done interrupt
0:Disable USB Transfer Done interrupt
Reserved
Write all reserved bits with ’0’.
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field | VBUS Interrupt | ID Interrupt |
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| Reserved |
| SOF/EOP | Reserved | |
Flag | Flag |
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| Interrupt Flag |
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Read/Write | R/W | R/W | - | - |
| - | - | R/W | - |
Default | X | X | X | X |
| X | X | X | X |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Port B | Port A | Port B Connect | Port A Connect | Port B | Port A | Reserved | Done Interrupt |
Field | Wake Interrupt | Wake Interrupt | Change | Change Interrupt | SE0 | SE0 |
| Flag |
Flag | Flag | Interrupt Flag | Flag | Status | Status |
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| |
Read/Write | R/W | R/W | R/W | R/W | R/W | R/W | - | R/W |
Default | X | X | X | X | X | X | X | X |
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Register Description
The Host n Status register provides status information for host operation. Pending interrupts can be cleared by writing a ‘1’ to the corresponding bit. This register can be accessed by the HPI interface.
VBUS Interrupt Flag (Bit 15)
The VBUS Interrupt Flag bit indicates the status of the OTG VBUS interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of VBUS at 4.4V. This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Interrupt triggered
0:Interrupt did not trigger
ID Interrupt Flag (Bit 14)
The ID Interrupt Flag bit indicates the status of the OTG ID interrupt (only for Port 1A). When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin. This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Interrupt triggered
0:Interrupt did not trigger
Document #: | Page 35 of 99 |
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