CY7C67300
Document #: 38-08015 Rev. *J Page 2 of 99
Introduction
EZ-Host™ (CY7C67300) is Cypress Semiconductor’s first
full-speed, low cost multiport host/peripheral controller. EZ-Host
is designed to easily interface to most high performance CPUs
to add USB host functionality. EZ-Host has its own 16-bit RISC
processor to act as a coprocessor or operate in standalone
mode. EZ-Host also has a programmable IO interface block
allowing a wide range of interface options.
Functional Overview
An overview of the processor core components are presented in
this section.
Processor Core
EZ-Host has a general purpose 16-bit embedded RISC
processor that runs at 48 MHz.
Clocking
EZ-Host requires a 12 MHz source for clocking. Either an
external crystal or TTL level oscillator may be used. EZ-Host has
an internal PLL that produces a 48 MHz internal clock from the
12 MHz source.
Memory
EZ-Host has a built in 4K × 16 masked ROM and an 8K × 16
internal RAM. The masked ROM contains the EZ-Host BIOS.
The internal RAM can be used for program code or data.
Interrupts
EZ-Host provides 128 interrupt vectors. The first 48 vectors are
hardware interrupts and the following 80 vectors are software
interrupts.
General Timers and Watchdog Timer
EZ-Host has two built in programmable timers and a Watchdog
timer. All three timers can generate an interrupt to the EZ-Host.
Power Management
EZ-Host has one main power saving mode, Sleep. Sleep mode
pauses all operations and provides the lowest power state.
Interface Descriptions
EZ-Host has a wide variety of interface options for connectivity.
With several interface options available, EZ-Host can act as a
seamless data transport between many different types of
devices.
See Table1 and Table 2o n page3 to understand how the inter-
faces share pins and which can coexist. Note that some inter-
faces have more then one possible port location selectable
through the GPIO control register [0xC006]. General guidelines
for interfaces are as follows:
■HPI and IDE interfaces are mutually exclusive.
■If 16-bit external memory is required, then HSS and SPI default
locations must be used.
■I2C EEPROM and OTG do not conflict with any interfaces.
Note
1. Default interface location.
Table 1. Interface Options for GPIO Pins
GPIO Pins HPI IDE PWM HSS SPI UART I2C OTG
GPIO31 SCL/SDA
GPIO30 SCL/SDA
GPIO29 OTGID
GPIO28 TX
GPIO27 RX
GPIO26 PWM3 CTS[1]
GPIO25
GPIO24 INT IOREADY
GPIO23 nRD IOR
GPIO22 nWR IOW
GPIO21 nCS
GPIO20 A1 CS1
GPIO19 A0 CS0
GPIO18 A2 PWM2 RTS[1]
GPIO17 A1 PWM1 RXD[1]
GPIO16 A0 PWM0 TXD[1]
GPIO15 D15 D15
GPIO14 D14 D14
GPIO13 D13 D13
GPIO12 D12 D12
GPIO11 D11 D11 MOSI[1]
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