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CY7C67300
Table 131. Pin Descriptions (continued) |
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Pin | Name |
| Type | Description |
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71 | D11/MOSI |
| IO | D11: External Memory Data Bus |
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| MOSI: SPI MOSI |
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72 | D10/SCK |
| IO | D10: External Memory Data Bus |
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| SCK: SPI SCK |
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73 | D9/nSSI |
| IO | D9: External Memory Data Bus |
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| nSSI: SPI nSSI |
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74 | D8/MISO |
| IO | D8: External Memory Data Bus |
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| MISO: SPI MISO |
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76 | D7 |
| IO | External Memory Data Bus |
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77 | D6 |
| IO |
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78 | D5 |
| IO |
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79 | D4 |
| IO |
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80 | D3 |
| IO |
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81 | D2 |
| IO |
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82 | D1 |
| IO |
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83 | D0 |
| IO |
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33 | A14 |
| Output | External Memory Address Bus |
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32 | A13 |
| Output |
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31 | A12 |
| Output |
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30 | A11 |
| Output |
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27 | A10 |
| Output |
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25 | A9 |
| Output |
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24 | A8 |
| Output |
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20 | A7 |
| Output |
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17 | A6 |
| Output |
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8 | A5 |
| Output |
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7 | A4 |
| Output |
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3 | A3 |
| Output |
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2 | A2 |
| Output |
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1 | A1 |
| Output |
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99 | nBEL/A0 |
| Output | nBEL: Low Byte Enable for |
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| A0: External Memory Address bit A0 for |
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98 | nBEH |
| Output | High Byte Enable for |
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64 | nWR |
| Output | External Memory Write pulse |
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62 | nRD |
| Output | External Memory Read pulse |
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97 | A16 |
| Output | A16: External SRAM A16 |
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96 | A17 |
| Output | A17: External SRAM A17 |
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95 | A18 |
| Output | A18: External SRAM A18 |
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34 | nXMEMSEL |
| Output | External Memory Select 0 |
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35 | nXROMSEL |
| Output | External Memory Select 1 |
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36 | nXRAMSEL |
| Output | External Memory Select 2 |
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38 | A15/CLKSEL |
| IO | A15: External SRAM A15 |
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| CLKSEL: Sampled directly after reset to determine what crystal or |
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| clock source frequency is being used. 12 MHz is required for normal |
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| operation so the CLKSEL pin must have a 47K ohm pull up to VCC. |
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| After reset this pin functions as A15. |
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39 | GPIO31/SCK |
| IO | GPIO31: General Purpose IO |
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| SCK: I2C EEPROM SCK |
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40 | GPIO30/SDA |
| IO | GPIO30: General Purpose IO |
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| SDA: I2C EEPROM SDA |
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Document #: |
| Page 80 of 99 |
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