Cypress CY7C67300 Host Port Interface, IDE Interface, HPI Interface Pins 3 Pin Name Pin Number

CY7C67300

Host Port Interface

EZ-Host has an HPI interface. The HPI interface provides DMA access to the EZ-Host internal memory by an external host, plus a bidirectional mailbox register for supporting high level commu- nication protocols. This port is designed to be the primary high-speed connection to a host processor. Complete control of EZ-Host can be accomplished through this interface via an extensible API and communication protocol. Other than the hardware communication protocols, a host processor has identical control over EZ-Host whether connecting to the HPI or HSS port. The HPI interface is exposed through GPIO pins.

HPI Features

■16-bit data bus interface

■16 MB/s throughput

■Auto-increment of address pointer for fast block mode transfers

■Direct memory access (DMA) to internal memory

■Bidirectional Mailbox register

■Byte swapping

■Complete access to internal memory

■Complete control of SIEs through HPI

■Dedicated HPI status register

HPI Pins

Table 12. HPI Interface Pins [3, 4]

Pin Name	Pin Number
INT	46
nRD	47
nWR	48
nCS	49
A1	50
A0	52
D15	56
D14	57
D13	58
D12	59

Table 12. HPI Interface Pins (continued)[3, 4]

D11	60
D10	61
D9	65
D8	66
D7	86
D6	87
D5	89
D4	90
D3	91
D2	92
D1	93
D0	94

The two HPI address pins are used to address one of four possible HPI port registers as shown in Table 13.

Table 13. HPI Addressing

HPI A[1:0]	A1	A0
HPI Data	0	0
HPI Mailbox	0	1
HPI Address	1	0
HPI Status	1	1

IDE Interface

EZ-Host has an IDE interface. The IDE interface supports PIO mode 0-4 as specified in the Information Technology-AT Attachment–4 with Packet Interface Extension (ATA/ATAPI-4) Specification, T13/1153D Rev 18. There is no need for firmware to use programmable wait states. The CPU read/write cycle is automatically extended as needed for direct CPU to IDE read/write accesses.

The EZ-Host IDE interface also has a BLOCK transfer mode that allows EZ-Host to read/write large blocks of data to/from the IDE data register and move it to/from the EZ-Host on-chip memory directly without intervention of the CPU. The IDE interface is exposed through GPIO pins. Table 14 on page 10 lists the achieved throughput for maximum block mode data transfer rate (with IDE_IORDY true) for the various IDE PIO modes.

Notes

3.HPI_INT is for the Outgoing Mailbox interrupt.

4.HPI strobes are negative logic sampled on rising edge.

Document #: 38-08015 Rev. *J Page 9 of 99

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