CY7C67300
Receive Bit Length (Bits [2:0])
The Receive Bit Length field controls whether a full byte or partial byte is received. If Receive Bit Length is ‘000’ then a full byte is received. If Receive Bit Length is ‘001’ to ‘111’, then the value indicates the number of bits that are received.
SPI Interrupt Enable Register [0xC0CC] [R/W]
Table 108. SPI Interrupt Enable Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
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| Reserved... |
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Read/Write | - | - | - | - |
| - | - | - | - |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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| ...Reserved |
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| Receive | Transmit | Transfer |
Field |
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| Interrupt | Interrupt | Interrupt |
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| Enable | Enable | Enable | |
Read/Write | - | - | - | - | - | R/W | R/W | R/W |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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Register Description
The SPI Interrupt Enable register controls the SPI port.
Receive Interrupt Enable (Bit 2)
The Receive Interrupt Enable bit enables or disables the byte mode receive interrupt (RxIntVal).
1:Enable byte mode receive interrupt
0:Disable byte mode receive interrupt
Transmit Interrupt Enable (Bit 1)
The Transmit Interrupt Enable bit enables or disables the byte mode transmit interrupt (TxIntVal).
SPI Status Register [0xC0CE] [R]
Table 109. SPI Status Register
1:Enables byte mode transmit interrupt
0:Disables byte mode transmit interrupt
Transfer Interrupt Enable (Bit 0)
The Transfer Interrupt Enable bit enables or disables the block mode interrupt (XfrBlkIntVal).
1:Enables block mode interrupt
0:Disables block mode interrupt
Reserved
Write all reserved bits with ’0’.
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
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| Reserved |
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| |
Read/Write | - | - | - | - |
| - | - | - | - |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 |
| 4 | 3 | 2 | 1 | 0 |
| FIFO Error |
| Reserved |
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| Receive | Transmit | Transfer | |
Field | Flag |
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| Interrupt | Interrupt | Interrupt |
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| Flag | Flag | Flag | |
Read/Write | R | - | - |
| - | - | R | R | R |
Default | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 |
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Register Description
The SPI Status register is a read only register that provides status for the SPI port.
FIFO Error Flag (Bit 7)
The FIFO Error Flag bit is a read only bit that indicates if a FIFO error occurred. When this bit is set to ‘1’ and the Transmit Empty
bit of the SPI Control register is set to ‘1’, then a Tx FIFO underflow occurred. Similarly, when set with the Receive Full bit of the SPI Control register, an Rx FIFO overflow occured.This bit automatically clears when the SPI FIFO Init Enable bit of the SPI Control register is set.
1:Indicates FIFO error
0:Indicates no FIFO error
Document #: | Page 68 of 99 |
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