CY7C67300
AC Timing Characteristics
Reset Timing
tRESET
nRESET
nRD or nWRL or nWRH
tIOACT
Reset Timing
Table 135. Reset Timing Parameters
Parameter | Description | Min | Typical | Max | Unit |
tRESET | nRESET Pulse Width | 16 |
|
| clocks[11] |
tIOACT | nRESET HIGH to nRD or nWRx active | 200 |
|
| µs |
Clock Timing
tCLK
XTALIN
tHIGH
tLOW
tFALL
tRISE
Clock Timing
Table 136. Clock Timing Parameters
Parameter | Description | Min | Typical | Max | Unit |
fCLK | Clock Frequency |
| 12.0 |
| MHz |
vXINH[12] | Clock Input High | 1.5 | 3.0 | 3.6 | V |
| (XTALOUT left floating) |
|
|
|
|
tCLK | Clock Period | 83.17 | 83.33 | 83.5 | ns |
tHIGH | Clock High Time | 36 |
| 44 | ns |
tLOW | Clock Low Time | 36 |
| 44 | ns |
tRISE | Clock Rise Time |
|
| 5.0 | ns |
tFALL | Clock Fall Time |
|
| 5.0 | ns |
Duty Cycle |
| 45 |
| 55 | % |
|
|
|
|
|
|
Notes
11.Clock is 12 MHz nominal.
12.vXINH is required to be 3.0 V to obtain an internal 50/50 duty cycle clock.
Document #: | Page 85 of 99 |
[+] Feedback
