CY7C67300
underflow and the Overflow and Underflow flags (bits 11 and 10 respectively) must be checked to determine which event occurred.
1:An overflow or underflow condition occurred
0:An overflow or underflow condition did not occur
Setup Flag (Bit 4)
The Setup Flag bit indicates that a setup packet was received. In device mode setup packets are stored at memory location 0x0300 for Device 1 and 0x0308 for Device 2. Setup packets are always accepted regardless of the Direction Select and Arm Enable bit settings as long as the Device n EP n Control register Enable bit is set.
1:Setup packet was received
0:Setup packet was not received
Sequence Flag (Bit 3)
The Sequence Flag bit indicates whether the last data toggle received was a DATA1 or a DATA0. This bit has no effect on receiving data packets; sequence checking must be handled in firmware.
1:DATA1 was received
0:DATA0 was received
Device n Endpoint n Count Result Register [R/W]
Timeout Flag (Bit 2)
The Timeout Flag bit indicates whether a timeout condition occurred on the last transaction. On the device side, a timeout can occur if the device sends a data packet in response to an IN request but then does not receive a handshake packet in a predetermined time. It can also occur if the device does not receive the data stage of an OUT transfer in time.
1:Timeout occurred
0:Timeout condition did not occur
Error Flag (Bit 2)
The Error Flag bit is set if a CRC5 and CRC16 error occurs, or if an incorrect packet type is received. Overflow and underflow are not considered errors and do not affect this bit.
1:Error occurred
0:Error did not occur
ACK Flag (Bit 0)
The ACK Flag bit indicates whether the last transaction was ACKed.
1:ACK occurred
0:ACK did not occur
■Device n Endpoint 0 Count Result Register [Device 1: 0x0208 Device 2: 0x0288]
■Device n Endpoint 1 Count Result Register [Device 1: 0x0218 Device 2: 0x0298]
■Device n Endpoint 2 Count Result Register [Device 1: 0x0228 Device 2: 0x02A8]
■Device n Endpoint 3 Count Result Register [Device 1: 0x0238 Device 2: 0x02B8]
■Device n Endpoint 4 Count Result Register [Device 1: 0x0248 Device 2: 0x02C8]
■Device n Endpoint 5 Count Result Register [Device 1: 0x0258 Device 2: 0x02D8]
■Device n Endpoint 6 Count Result Register [Device 1: 0x0268 Device 2: 0x02E8]
■Device n Endpoint 7 Count Result Register [Device 1: 0x0278 Device 2: 0x02F8]
Table 67. Device n Endpoint n Count Result Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
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|
|
| Result... |
|
|
| |
Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | X | X | X | X |
| X | X | X | X |
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Bit # | 7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Field |
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|
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| ...Result |
|
|
| |
Read/Write | R/W | R/W | R/W | R/W |
| R/W | R/W | R/W | R/W |
Default | X | X | X | X |
| X | X | X | X |
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Register Description
The Device n Endpoint n Count Result register contains the size difference in bytes between the Endpoint Count specified in the Device n Endpoint n Count register and the last packet received. If an overflow or underflow condition occurs, that is, the received packet length differs from the value specified in the Device n
Endpoint n Count register, the Length Exception Flag bit in the Device n Endpoint n Status register is set. The value in this register is only valued when the Length Exception Flag bit is set and the Error Flag bit is not set; both bits are in the Device n Endpoint n Status register.
Document #: | Page 42 of 99 |
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