CY7C67300
Host n Device Address Register [W]
■Host 1 Device Address Register 0xC088
■Host 2 Device Address Register 0xC0A8
Table 56. Host n Device Address Register
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
Field |
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| Reserved... |
|
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| |
Read/Write | - | - | - | - |
| - | - | - | - |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Field | ...Reserved |
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| Address |
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|
Read/Write | - | W | W | W | W | W | W | W |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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Register Description
The Host n Device Address register is a write only register that contains the USB Device Address that the host wants to commu- nicate with.
Host n Interrupt Enable Register [R/W]
■Host 1 Interrupt Enable Register 0xC08C
■Host 2 Interrupt Enable Register 0xC0AC
Table 57. Host n Interrupt Enable Register
Address (Bits [6:0])
The Address field contains the value of the USB address for the next device that the host is going to communicate with. This value must be written by firmware.
Reserved
Write all reserved bits with ’0’.
Bit # | 15 | 14 | 13 | 12 |
| 11 | 10 | 9 | 8 |
| VBUS | ID Interrupt |
| Reserved |
|
| SOF/EOP | Reserved | |
Field | Interrupt | Enable |
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| Interrupt |
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Enable |
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| Enable |
| |
Read/Write | R/W | R/W | - | - |
| - | - | R/W | - |
Default | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 |
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Bit # | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| Port B | Port A | Port B Connect | Port A Connect |
| Reserved |
| Done |
| Wake Interrupt | Wake Interrupt | Change | Change |
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| Interrupt |
Field | Enable | Enable | Interrupt | Interrupt |
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| Enable |
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| Enable | Enable |
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| |
Read/Write | R/W | R/W | R/W | R/W | - | - | - | R/W |
Default | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
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Register Description
The Host n Interrupt Enable register enables control over host related interrupts.
In this register a bit set to ‘1’ enables the corresponding interrupt while ‘0’ disables the interrupt.
VBUS Interrupt Enable (Bit 15)
The VBUS Interrupt Enable bit enables or disables the OTG VBUS interrupt. When enabled this interrupt triggers on both the rising and falling edge of VBUS at the 4.4V status (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Enable VBUS interrupt
0:Disable VBUS interrupt
ID Interrupt Enable (Bit 14)
The ID Interrupt Enable bit enables or disables the OTG ID interrupt. When enabled this interrupt triggers on both the rising and falling edge of the OTG ID pin (only supported in Port 1A). This bit is only available for Host 1 and is a reserved bit in Host 2.
1:Enable ID interrupt
0:Disable ID interrupt
Document #: | Page 34 of 99 |
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