Freescale Semiconductor MC68HC908MR32 Break Status and Control Register, Brka Break Active Bit

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18.2.3.1 Break Status and Control Register

The break status and control register (BRKSCR) contains break module enable and status bits.

Address:

Read:

Write:

Reset:

$FE0E
Bit 7	6	5	4	3	2	1	Bit 0
BRKE	BRKA	0	0	0	0	0	0
0	0	0	0	0	0	0	0
	= Unimplemented

Figure 18-3. Break Status and Control Register (BRKSCR)

BRKE — Break Enable Bit

This read/write bit enables breaks on break address register matches. Clear BRKE by writing a logic 0 to bit 7. Reset clears the BRKE bit.

1= Breaks enabled on 16-bit address match

0= Breaks disabled on 16-bit address match

BRKA — Break Active Bit

This read/write status and control bit is set when a break address match occurs. Writing a logic 1 to BRKA generates a break interrupt. Clear BRKA by writing a logic 0 to it before exiting the break routine. Reset clears the BRKA bit.

1 = When read, break address match

0 = When read, no break address match

18.2.3.2 Break Address Registers

The break address registers (BRKH and BRKL) contain the high and low bytes of the desired breakpoint address. Reset clears the break address registers.

Address:	$FE0C
	Bit 7	6	5	4	3	2	1	Bit 0
Read:
	Bit 15	14	13	12	11	10	9	Bit 8
Write:
Reset:	0	0	0	0	0	0	0	0
	Figure 18-4. Break Address Register High (BRKH)
Address:	$FE0D
	Bit 7	6	5	4	3	2	1	Bit 0
Read:
	Bit 7	6	5	4	3	2	1	Bit 0
Write:
Reset:	0	0	0	0	0	0	0	0

Figure 18-5. Break Address Register Low (BRKL)

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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