Freescale Semiconductor MC68HC908MR16 manual LVI Status and Control Register, LVI Interrupts

LVI Status and Control Register

9.4 LVI Status and Control Register

The LVI status register (LVISCR) flags VDD voltages below the VLVRX level.

Address:	$FE0F
	Bit 7	6	5	4	3	2	1	Bit 0
Read:	LVIOUT	0	TRPSEL	0	0	0	0	0
Write:	R	R		R	R	R	R	R
Reset:	0	0	0	0	0	0	0	0
	R	= Reserved

Figure 9-3. LVI Status and Control Register (LVISCR)

LVIOUT — LVI Output Bit

This read-only flag becomes set when the VDD voltage falls below the VLVRX voltage for 32 to 40 CGMXCLK cycles. See Table 9-1.Reset clears the LVIOUT bit.

Table 9-1. LVIOUT Bit Indication

	VDD	LVIOUT
At Level:	For Number of CGMXCLK Cycles:
VDD > VLVRX + VLVHX	Any	0
VDD < VLVRX	< 32 CGMXCLK cycles	0
VDD < VLVRX	Between 32 & 40 CGMXCLK cycles	0 or 1
VDD < VLVRX	> 40 CGMXCLK cycles	1
VLVRX < VDD < VLVRX + VLVHX	Any	Previous value

TRPSEL — LVI Trip Select Bit

This bit selects the LVI trip point. Reset clears this bit.

1 = 5 percent tolerance. The trip point and recovery point are determined by VLVR1 and VLVH1, respectively.

0 = 10 percent tolerance. The trip point and recovery point are determined by VLVR2 and VLVH2, respectively.

NOTE

If LVIRST and LVIPWR are 0s, note that when changing the tolerance, LVI reset will be generated if the supply voltage is below the trip point.

9.5 LVI Interrupts

The LVI module does not generate interrupt requests.

9.6 Wait Mode

The WAIT instruction puts the MCU in low power-consumption standby mode.

With the LVIPWR bit in the configuration register programmed to 1, the LVI module is active after a WAIT instruction.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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