I/O Registers

13.7.3 SCI Control Register 3

SCI control register 3 (SCC3):

•Stores the ninth SCI data bit received and the ninth SCI data bit to be transmitted

•Enables SCI receiver full (SCRF)

•Enables SCI transmitter empty (SCTE)

•Enables the following interrupts:

–Receiver overrun interrupts

–Noise error interrupts

–Framing error interrupts

–Parity error interrupts

Address:

$003A

 

 

 

 

 

 

 

 

 

Bit 7

6

5

4

3

 

2

1

Bit 0

 

 

 

 

 

 

 

 

 

 

Read:

R8

T8

0

0

ORIE

 

NEIE

FEIE

PEIE

 

 

 

 

 

Write:

R

R

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Reset:

U

U

0

0

0

 

0

0

0

 

 

 

 

 

 

 

 

 

 

 

R

= Reserved

 

 

U = Unaffected

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 13-10. SCI Control Register 3 (SCC3)

R8 — Received Bit 8

When the SCI is receiving 9-bit characters, R8 is the read-only ninth bit (bit 8) of the received character. R8 is received at the same time that the SCDR receives the other eight bits.

When the SCI is receiving 8-bit characters, R8 is a copy of the eighth bit (bit 7). Reset has no effect on the R8 bit.

T8 — Transmitted Bit 8

When the SCI is transmitting 9-bit characters, T8 is the read/write ninth bit (bit 8) of the transmitted character. T8 is loaded into the transmit shift register at the same time that the SCDR is loaded into the transmit shift register. Reset has no effect on the T8 bit.

ORIE — Receiver Overrun Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the receiver overrun bit, OR. 1 = SCI error CPU interrupt requests from OR bit enabled

0 = SCI error CPU interrupt requests from OR bit disabled

NEIE — Receiver Noise Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the noise error bit, NE. Reset clears NEIE.

1 = SCI error CPU interrupt requests from NE bit enabled

0 = SCI error CPU interrupt requests from NE bit disabled

FEIE — Receiver Framing Error Interrupt Enable Bit

This read/write bit enables SCI error CPU interrupt requests generated by the framing error bit, FE. Reset clears FEIE.

1 = SCI error CPU interrupt requests from FE bit enabled

0 = SCI error CPU interrupt requests from FE bit disabled

PEIE — Receiver Parity Error Interrupt Enable Bit

This read/write bit enables SCI receiver CPU interrupt requests generated by the parity error bit, PE. See 13.7.4 SCI Status Register 1. Reset clears PEIE.

1 = SCI error CPU interrupt requests from PE bit enabled

0 = SCI error CPU interrupt requests from PE bit disabled

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor

173

Page 172 Page 174
Page 173
Image 173
Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual T8 Transmitted Bit, Orie Receiver Overrun Interrupt Enable Bit
Page 172 Page 174

MC68HC908MR16, MC68HC908MR32 specifications

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