MC68HC908MR32 MC68HC908MR16
Page
 Data Sheet
MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev
MC68HC908MR32 MC68HC908MR16
 Revision History
Revision History
Date Revision Description Level Numbers
 List of Chapters
 List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev
 Table of Contents
 Table of Contents
Chapter Analog-to-Digital Converter ADC
Chapter Clock Generator Module CGM
 Chapter Computer Operating Properly COP
Chapter Configuration Register Config
 Chapter Central Processor Unit CPU
Chapter External Interrupt IRQ
Chapter Low-Voltage Inhibit LVI
 Chapter Power-On Reset POR
Chapter Input/Output I/O Ports Ports
Chapter Pulse-Width Modulator for Motor Control Pwmmc
 Chapter Serial Communications Interface Module SCI
 Chapter Serial Peripheral Interface Module SPI
Chapter System Integration Module SIM
 Chapter Timer Interface a Tima
 Chapter Development Support
Chapter Timer Interface B Timb
 Chapter Ordering Information and Mechanical Specifications
Chapter Electrical Specifications
 Features
Chapter General Description
Introduction
 General Description
MCU Block Diagram
 MCU Block
Diagram
 Pin QFP Pin Assignments
Pin Assignments
 Pin Assignments
Pin Sdip Pin Assignments
 CGM Power Supply Pins Vdda and Vssad
Power Supply Pins VDD and VSS
Oscillator Pins OSC1 and OSC2
External Reset Pin RST
 Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8
Analog Power Supply Pins Vddad and Vssad
Port a Input/Output I/O Pins PTA7-PTA0
Port B I/O Pins PTB7/ATD7-PTB0/ATD0
 PWM Ground Pin Pwmgnd
Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK
 Chapter Memory
Unimplemented Memory Locations
Reserved Memory Locations
 I/O Section
Memory Map
Memory
 Memory Map
MC68HC908MR32 Memory Map
 Memory Addr
Control, Status, and Data Registers Summary Sheet 1
 Memory Map Addr Register Name Bit
Control, Status, and Data Registers Summary Sheet 2
 Memory Addr Register Name
Control, Status, and Data Registers Summary Sheet 3
 Control, Status, and Data Registers Summary Sheet 4
 Memory Addr Register Name Bit
Control, Status, and Data Registers Summary Sheet 5
 Addr Register Name
Control, Status, and Data Registers Summary Sheet 6
 Control, Status, and Data Registers Summary Sheet 7
 Control, Status, and Data Registers Summary Sheet 8
 Address Vector Low
Vector Addresses
 Address Vector
Random-Access Memory RAM
Monitor ROM
Monitor ROM
 Flash Control Register
Flash Memory Flash
 Erase Erase Control Bit
Hven High-Voltage Enable Bit
Flash Page Erase Operation
Mass Mass Erase Control Bit
 Flash Mass Erase Operation
 Only bytes which are currently $FF may be programmed
Flash Program Operation
 Flash Programming Flowchart
 Flash Block Protect Register
Flash Block Protection
 Wait Mode
Stop Mode
Examples of Protect Start Address
 Functional Description
Chapter Analog-to-Digital Converter ADC
 Analog-to-Digital Converter ADC
Block Diagram Highlighting ADC Block and Pins
 ADC Port I/O Pins
Voltage Conversion
Functional Description
 Conversion Time
Continuous Conversion
Result Justification
 Monotonicity
Bit Truncation Mode Error
 Wait Mode
I/O Signals
Interrupts
 6.2 ANx
I/O Registers
ADC Voltage In Advin
ADC External Connections
 ADC Status and Control Register
Aien ADC Interrupt Enable Bit
 Input Select
Mux Channel Select
 ADC Data Register Low
ADC Data Register High
 ADC Clock Register
ADC Clock Divide Ratio
ADC Clock Rate
 Analog-to-Digital Converter ADC
 Cgmvclk
Chapter Clock Generator Module CGM
 Clock Generator Module CGM
CGM Block Diagram
 Phase-Locked Loop Circuit PLL
Crystal Oscillator Circuit
PLL Circuits
 Manual and Automatic PLL Bandwidth Modes
Acquisition and Tracking Modes
 Programming the PLL
Variable Definitions
Variable Definition
 Special Programming Exceptions
Base Clock Selector Circuit
 CGM External Connections
CGM External Connections
 Crystal Amplifier Output Pin OSC2
PLL Analog Power Pin Vdda
Oscillator Enable Signal Simoscen
Crystal Amplifier Input Pin OSC1
 CGM CPU Interrupt Cgmint
Crystal Output Frequency Signal Cgmxclk
CGM Registers
CGM Base Clock Output Cgmout
 BCS Base Clock Select Bit
PLL Control Register
Pllf PLL Interrupt Flag
Pllon PLL On Bit
 PCTL30 Unimplemented Bits
Lock Lock Indicator Bit
ACQ Acquisition Mode Bit
PLL Bandwidth Control Register
 VCO Frequency Multiplier N Selection
PLL Programming Register
XLD Crystal Loss Detect Bit
PBWC30 Reserved for Test
 Interrupts
VRS74 VCO Range Select Bits
 Acquisition/Lock Time Specifications
Acquisition/Lock Time Definitions
Parametric Influences on Reaction Time
 Acquisition/Lock Time Specifications
Choosing a Filter Capacitor
Reaction Time Calculation
 Frequency
 Chapter Configuration Register Config
 Configuration Register
 Chapter Computer Operating Properly COP
COP Block Diagram
 Copctl Write
Power-On Reset
Internal Reset
Reset Vector Fetch
 COP Control Register
Monitor Mode
Stop Mode
Copd COP Disable
 Freescale Semiconductor
 CPU Registers
Chapter Central Processor Unit CPU
 Accumulator
Index Register
Central Processor Unit CPU
 Stack Pointer
Program Counter
CPU Registers
 Negative Flag
Condition Code Register
Half-Carry Flag
Interrupt Mask
 Zero Flag
Low-Power Modes
Arithmetic/Logic Unit ALU
CPU During Break Interrupts
 Instruction Set Summary Sheet 1
Instruction Set Summary
 Instruction Set Summary Sheet 2
Instruction Set Summary
Source Operation Description On CCR Form
 Dbnz opr,rel
Instruction Set Summary Sheet 3
 JMP ,X
Instruction Set Summary Sheet 4
 Operation Description On CCR Form
Instruction Set Summary Sheet 5
 Opcode Map
Instruction Set Summary Sheet 6
Opcode Map
 9ED 9EE
Opcode Map
 Chapter External Interrupt IRQ
IRQ Module Block Diagram
 External Interrupt IRQ
IRQ Pin
 IRQ Pin
IRQ Interrupt Flowchart
 IRQ Status and Control Register Iscr
IRQ Status and Control Register
 IRQ Status and Control Register
Irqf IRQ Flag
 Freescale Semiconductor
 Chapter Low-Voltage Inhibit LVI
LVI Module Block Diagram
 LVI Trip Selection
Forced Reset Operation
False Reset Protection
Polled LVI Operation
 LVI Status and Control Register
LVI Status and Control Register
LVI Interrupts
Lviout Bit Indication
 100 Freescale Semiconductor
 I/O Port Register Summary
Chapter Input/Output I/O Ports Ports
 Input/Output I/O Ports Ports Addr Register Name
 Port a
Port a
Port a Data Register
Data Direction Register a
 Input/Output I/O Ports Ports
Port B
Port B Data Register
Port a Pin Functions
 Data Direction Register B
Port B Pin Functions
Port B
 Port C
Port C Data Register
Data Direction Register C
 PTC60
Port D
Port C Pin Functions
Port D
 Port D Pin Functions
PTD Bit Pin Mode Accesses to PTD Read
Port E
Port E Data Register
 Port E
Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTE
Data Direction Register E
Port E Pin Functions
 Port F
Port F Data Register
Data Direction Register F
 Port F
Port F Pin Functions
 112 Freescale Semiconductor
 Chapter Power-On Reset POR
 114 Freescale Semiconductor
 Chapter Pulse-Width Modulator for Motor Control Pwmmc
 Pulse-Width Modulator for Motor Control Pwmmc
Block Diagram Highlighting Pwmmc Block and Pins
 Features
PWM Module Block Diagram
 Register Summary Sheet 2
 Register Summary Sheet 3
Features Addr Register Name Bit
 Timebase
Resolution
 Timebase
Edge-Aligned PWM Positive Polarity
 PWM Prescaler
PWM Generators
Prescaler
Load Operation
 PWM Interrupt Requests
Reload Frequency Change
 Center-Aligned PWM Value Loading
 PWM Data Overflow and Underflow Conditions
PWM Data Overflow and Underflow Conditions
PWMVALxHPWMVALxL Condition PWM Value Used
 Output Control
12. Complementary Pairing
 Output Control
Dead-Time Insertion
 14. Dead-Time Generators
 15. Effects of Dead-Time Insertion
 17. Dead-Time and Small Pulse Widths
 Current Voltage On Current
Current Sense Pins
 Current Correction Bits Correction Method ISENS1 and ISENS0
Correction Methods
 20. Top/Bottom Correction for PWMs 1
Output Polarity
 21. PWM Polarity
 OUTx Bit Complementary Mode Independent Mode
PWM Output Port Control
OUTx Bits
 23. Dead-Time Insertion During Outctl =
 Fault Protection
Fault Condition Input Pins
Fault Protection
 26. PWM Disabling Scheme
 Automatic Mode
Fault Pin Filter
 Manual Mode
28. PWM Disabling in Automatic Mode
 Output Port Control
Software Output Disable
 Initialization and the Pwmen Bit
32. Pwmen and PWM Pins
 PWM Counter Registers
PWM Operation in Wait Mode
PWM Operation in Wait Mode
Control Logic Block
 35. PWM Counter Modulo Register High Pmodh
PWM Counter Modulo Registers
 Control Logic Block
PWMx Value Registers
 Pwmf PWM Reload Flag
Disy Software Disable Bit for Bank Y Bit
Pwmint PWM Interrupt Enable Bit
PWM Control Register
 LDOK- Load OK Bit
Pwmen PWM Module Enable Bit
 IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1
 IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3
IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5
PRSC1 and PRSC0 PWM Prescaler Bits
 PWM Disable Mapping Write-Once Register
Fault Control Register
Dead-Time Write-Once Register
 FINT3 Fault 3 Interrupt Enable Bit
FINT2 Fault 2 Interrupt Enable Bit
FINT1 Fault 1 Interrupt Enable Bit
 Fault Status Register
 Fault Acknowledge Register
 10. OUTx Bits
PWM Output Control Register
DT2 Dead-Time 2 Bit
DT1 Dead-Time 1 Bit
 PWM Glossary
PWM Glossary
 48. PWM Load Cycle/Frequency Definition
 Chapter Serial Communications Interface Module SCI
 Serial Communications Interface Module SCI
Block Diagram Highlighting SCI Block and Pins
 SCI Module Block Diagram
 Serial Communications Interface Module SCI Addr
Data Format
 SCI Transmitter
Transmitter
 Character Length
Character Transmission
Break Characters
 Transmitter Interrupts
Receiver
Idle Characters
Inversion of Transmitted Output
 SCI Receiver Block Diagram
 Data Sampling
Character Reception
 Data Bit Recovery
Stop Bit Recovery
Start Bit Verification
 Receiver Interrupts
Framing Errors
Error Interrupts
Receiver Wakeup
 13.6 I/O Signals
SCI During Break Module Interrupts
13.6.1 PTF5/TxD Transmit Data
 13.7 I/O Registers
13.6.2 PTF4/RxD Receive Data
SCI Control Register
 Txinv Transmit Inversion Bit
Ensci Enable SCI Bit
Mode Character Length Bit
PEN Parity Enable Bit
 Start Data Parity Stop
Tcie Transmission Complete Interrupt Enable Bit
Character Format Selection
Control Bits Character Format
 RE Receiver Enable Bit
Scrie SCI Receive Interrupt Enable Bit
Ilie Idle Line Interrupt Enable Bit
TE Transmitter Enable Bit
 Peie Receiver Parity Error Interrupt Enable Bit
Orie Receiver Overrun Interrupt Enable Bit
Neie Receiver Noise Error Interrupt Enable Bit
Feie Receiver Framing Error Interrupt Enable Bit
 SCI Status Register
TC Transmission Complete Bit
Scrf SCI Receiver Full Bit
 Or Receiver Overrun Bit
Idle Receiver Idle Bit
 FE Receiver Framing Error Bit
PE Receiver Parity Error Bit
NF Receiver Noise Flag Bit
 SCI Baud Rate Prescaling
SCI Data Register
SCI Baud Rate Register
RPF -Reception-in-Progress Flag
 Baud Rate Divisor BD
SCI Baud Rate Selection
 Baud Rate Divisor PD Divisor BD
SCI Baud Rate Selection Examples
 180 Freescale Semiconductor
 Signal Name Conventions
Signal Name Description
Chapter System Integration Module SIM
 System Integration Module SIM
Clock Startup from POR or LVI Reset
SIM Bus Clock Control and Generation
Bus Timing
 Reset and System Initialization
Reset and System Initialization
Clocks in Wait Mode
External Pin Reset
 Active Resets from Internal Sources
Reset Type Number of Cycles Required to Set PIN
PIN Bit Set Timing
 Computer Operating Properly COP Reset
Power-On Reset POR
 SIM Counter During Power-On Reset
SIM Counter and Reset States
SIM Counter
 Exception Control
Interrupts
Exception Control
 Interrupt Processing
 Hardware Interrupts
Interrupt Recovery
 Low-Power Mode
Reset
Software Interrupt SWI Instruction
 SIM Registers
SIM Break Status Register
SIM Registers
 Ilad Illegal Address Reset Bit opcode fetches only
SIM Reset Status Register
PIN External Reset Bit
Ilop Illegal Opcode Reset Bit
 SIM Break Flag Control Register
 194 Freescale Semiconductor
 Chapter Serial Peripheral Interface Module SPI
Pin Name Conventions
Pin Name Conventions
 Serial Peripheral Interface Module SPI
Block Diagram Highlighting SPI Block and Pins
 SPI Module Block Diagram
 Serial Peripheral Interface Module SPI Addr
Master Mode
 Transmission Formats
Slave Mode
Clock Phase and Polarity Controls
Transmission Formats
 Transmission Format Cpha =
Transmission Format When Cpha =
 Transmission Initiation Latency
 Transmission Start Delay Master
 Error Conditions
Overflow Error
Error Conditions
 10. Clearing Sprf When Ovrf Interrupt Is Not Enabled
Mode Fault Error
 Freescale Semiconductor 205
 Flag Request
SPI Interrupts
 Resetting the SPI
Resetting the SPI
Queuing Transmission Data
 12. SPRF/SPTE CPU Interrupt Timing
15.11 I/O Signals
 Spsck Serial Clock
Signals
Miso Master In/Slave Out
Mosi Master Out/Slave
 VSS Clock Ground
SPI Configuration
SPI Configuration State of SS Logic
15.12 I/O Registers
 Cpol Clock Polarity Bit
Cpha Clock Phase Bit
Spwom SPI Wired-OR Mode Bit
Spmstr SPI Master Bit
 SPI Status and Control Register
SPE SPI Enable Bit
SPTIE- SPI Transmit Interrupt Enable Bit
Errie Error Interrupt Enable Bit
 Spte SPI Transmitter Empty Bit
Modf Mode Fault Bit
Modfen Mode Fault Enable Bit
Ovrf Overflow Bit
 SPI Master Baud Rate Selection
SPI Data Register
 2is a block diagram of the Tima
Chapter Timer Interface a Tima
 Timer Interface a Tima
Block Diagram Highlighting Tima Block and Pins
 Tima Block Diagram
 TIM I/O Register Summary
Timer Interface a Tima Addr Register Name Bit
 Input Capture
Tima Counter Prescaler
 Unbuffered Output Compare
Output Compare
 Buffered Output Compare
Pulse-Width Modulation PWM
 PWM Period and Pulse Width
Unbuffered PWM Signal Generation
 PWM Initialization
Buffered PWM Signal Generation
 224 Freescale Semiconductor
 Tima Clock Pin PTE3/TCLKA
16.6 I/O Signals
Tima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A
16.7 I/O Registers
 Toie Tima Overflow Interrupt Enable Bit
Trst Tima Reset Bit
Tstop Tima Stop Bit
 PS20 Tima Clock Source
Tima Counter Registers
PS20 Prescaler Select Bits
Prescaler Selection
 Tima Channel Status and Control Registers
Tima Counter Modulo Registers
 CHxIE Channel x Interrupt Enable Bit
 MSxB Mode Select Bit B
MSxA Mode Select Bit a
ELSxB and ELSxA Edge/Level Select Bits
 CHxMAX Channel x Maximum Duty Cycle Bit
MSxBMSxA ELSxBELSxA Mode Configuration
Mode, Edge, and Level Selection
TOVx Toggle-On-Overflow Bit
 10. Tima Channel Registers
Tima Channel Registers
 10. Tima Channel Registers TACH0H/L-TACH3H/L
 234 Freescale Semiconductor
 Timb module is not available in the 56-pin Sdip
Chapter Timer Interface B Timb
 Timer Interface B Timb
Block Diagram Highlighting Timb Block and Pins
 Timb Block Diagram
 Timb Counter Prescaler
Timer Interface B Timb Addr Register Name Bit
 Freescale Semiconductor 239
 240 Freescale Semiconductor
 Freescale Semiconductor 241
 242 Freescale Semiconductor
 17.6 I/O Signals
Timb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B
Timb Clock Pin PTE0/TCLKB
 Toie Timb Overflow Interrupt Enable Bit
17.7 I/O Registers
Timb Status and Control Register
 Trst Timb Reset Bit
Tstop Timb Stop Bit
PS20 Timb Clock Source
 Timb Counter Modulo Registers
Timb Counter Registers
 Timb Channel Status and Control Registers
 248 Freescale Semiconductor
 PWM
 10. Timb Channel Registers TBCH0H/L-TBCH1H/L
Timb Channel Registers
 Flag Protection During Break Interrupts
Chapter Development Support
Break Module BRK
Functional Description
 Development Support
Break Module Block Diagram
 Break Module Registers
Low-Power Modes
 Break Status and Control Register
Brka Break Active Bit
Break Address Registers
 Monitor ROM MON
Monitor ROM MON
Break Status Register
Break Flag Control Register
 Entering Monitor Mode
Mode Differences
Normal Monitor Mode
 Monitor Mode Circuit
 $FFFF
Monitor Mode Signal Requirements and Options
 Data Format
Forced Monitor Mode
 Break Signal
Commands
Echoing
 Command Sequence
Read Read Memory Command
Write Write Memory Command
Iread Indexed Read Command
 Iwrite Indexed Write Command
Readsp Read Stack Pointer Command
RUN Run User Program Command
 Security
Baud Rate
Monitor Baud Rate Selection
 13. Monitor Mode Entry Timing
 Chapter Electrical Specifications
Characteristic1 Symbol Value Unit
Absolute Maximum Ratings
 Functional Operating Range
Thermal Characteristics
Electrical Specifications
Characteristic Symbol Value Unit
 DC Electrical Characteristics
DC Electrical Characteristics
Characteristic1 Symbol Min Typ2 Max Unit
 Control Timing
Flash Memory Characteristics
Characteristic Symbol Min Typ Max Unit
Characteristic Symbol Min Max Unit
 Serial Peripheral Interface Characteristics
Serial Peripheral Interface Characteristics
Diagram Characteristic2 Symbol Min Max Unit Number1
 SPI Master Timing
 SPI Slave Timing
 CGM Operating Conditions
TImer Interface Module Characteristics
Clock Generation Module Component Specifications
Characteristic Symbol Min Typ Max
 CGM Acquisition/Lock Time Specifications
CGM Acquisition/Lock Time Specifications
Description Symbol Min Typ Max
 3FF
Analog-to-Digital Converter ADC Characteristics
 MC Order Number Operating
Chapter Ordering Information and Mechanical Specifications
Order Numbers
Order Numbers
 20.3 64-Pin Plastic Quad Flat Pack QFP
Ordering Information and Mechanical Specifications
 Pin Shrink Dual In-Line Package Sdip
20.4 56-Pin Shrink Dual In-Line Package Sdip
 278 Freescale Semiconductor
 Appendix a MC68HC908MR16
 MC68HC908MR16
Figure A-1. MC68HC908MR16 Memory Map
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