SPE SPI Enable Bit | Freescale Semiconductor MC68HC908MR32 specification

Serial Peripheral Interface Module (SPI)

SPE — SPI Enable Bit

This read/write bit enables the SPI module. Clearing SPE causes a partial reset of the SPI. See 15.8 Resetting the SPI. Reset clears the SPE bit.

1 = SPI module enabled

0 = SPI module disabled

SPTIE— SPI Transmit Interrupt Enable Bit

This read/write bit enables CPU interrupt requests generated by the SPTE bit. SPTE is set when a byte transfers from the transmit data register to the shift register. Reset clears the SPTIE bit.

1 = SPTE CPU interrupt requests enabled

0 = SPTE CPU interrupt requests disabled

15.12.2 SPI Status and Control Register

The SPI status and control register (SPSCR) contains flags to signal these conditions:

•Receive data register full

•Failure to clear SPRF bit before next byte is received (overflow error)

•Inconsistent logic level on SS pin (mode fault error)

•Transmit data register empty

The SPI status and control register also contains bits that perform these functions:

•Enable error interrupts

•Enable mode fault error detection

•Select master SPI baud rate

Address:	$0045
	Bit 7	6	5	4	3	2	1	Bit 0

Read:	SPRF	ERRIE	OVRF	MODF	SPTE	MODFEN	SPR1	SPR0

Write:	R		R	R	R
Write:	R		R	R	R

Reset:	0	0	0	0	1	0	0	0

	R	= Reserved

Figure 15-15. SPI Status and Control Register (SPSCR)

SPRF — SPI Receiver Full Bit

This clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. SPRF generates a CPU interrupt request if the SPRIE bit in the SPI control register is set also.

During an SPRF CPU interrupt (DMAS = 0), the CPU clears SPRF by reading the SPI status and control register with SPRF set and then reading the SPI data register.

Reset clears the SPRF bit.

1 = Receive data register full

0 = Receive data register not full

ERRIE — Error Interrupt Enable Bit

This read/write bit enables the MODF and OVRF bits to generate CPU interrupt requests. Reset clears the ERRIE bit.

1 = MODF and OVRF can generate CPU interrupt requests.

0 = MODF and OVRF cannot generate CPU interrupt requests.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

212	Freescale Semiconductor

MC68HC908MR16, MC68HC908MR32 specifications

Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are part of the popular HC08 family, designed primarily for embedded applications. These microcontrollers are particularly favored in automotive, industrial, and consumer product sectors due to their reliability and versatility.

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In summary, Freescale Semiconductor's MC68HC908MR32 and MC68HC908MR16 microcontrollers are key players in the embedded systems landscape. Their blend of power efficiency, integrated features, and scalability ensures they remain relevant for a wide array of applications, making them a favored choice among engineers and developers looking for dependable solutions in a competitive market.

Freescale Semiconductor MC68HC908MR32 manual SPI Status and Control Register, SPE SPI Enable Bit

Models: MC68HC908MR16 MC68HC908MR32