Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 manual DC Electrical Characteristics

DC Electrical Characteristics

19.5 DC Electrical Characteristics

Characteristic(1)				Symbol	Min	Typ(2)	Max	Unit
Output high voltage				VOH	VDD –0.8	—	—	V
(ILoad = –2.0 mA) all I/O pins
Output low voltage				VOL	—	—	0.4	V
(ILoad = 1.6 mA) all I/O pins
PWM pin output source current				IOH	–7	—	—	mA
(VOH = VDD –0.8 V)
PWM pin output sink current (VOL = 0.8 V)				IOL	20	—	—	mA
Input high voltage, all ports,				VIH	0.7 x VDD	—	VDD	V
		IRQs, RESET, OSC1
Input low voltage, all ports,				VIL	VSS	—	0.3 x VDD	V
	IRQs, RESET, OSC1
VDD supply current
Run(3)				IDD	—	—	30	mA
Wait(4)					—	—	12	mA
Stop(5)					—	—	700	∝A
I/O ports high-impedance leakage current				IIL	—	—	±10	∝A
Input current (input only pins)				IIn	—	—	±1	∝A
Capacitance				COut	—	—	12	pF
Ports (as input or output)				CIn	—	—	8
Low-voltage inhibit reset(6)				VLVR1	4.0	4.35	4.65	V
Low-voltage reset/recover hysteresis				VLVH1	40	90	150	mV
Low-voltage inhibit reset recovery				VREC1	4.04	4.5	4.75	V
(VREC1 = VLVR1 + VLVH1)
Low-voltage inhibit reset				VLVR2	3.85	4.15	4.45	V
Low-voltage reset/recover hysteresis				VLVH2	150	210	250	mV
Low-voltage inhibit reset recovery				VREC2	4.0	4.4	4.6	V
(VREC2 = VLVR2 + VLVH2)
POR re-arm voltage(7)				VPOR	0	—	100	mV
POR rise time ramp rate(8)				RPOR	0.035	—	—	V/ms
POR reset voltage(9)				VPORRST	0	700	800	V
Monitor mode entry voltage (on				VHi	VDD + 2.5	—	8.0	V
			IRQ)

1.VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted.

2.Typical values reflect average measurements at midpoint of voltage range, 25°C only.

3.Run (operating) IDD measured using external square wave clock source (fOSC = 8.2 MHz). All inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects run IDD; measured with all modules enabled

4.Wait IDD measured using external square wave clock source (fOSC = 8.2 MHz); all inputs 0.2 V from rail; no dc loads; less than 100 pF on all outputs. CL = 20 pF on OSC2; all ports configured as inputs; OSC2 capacitance linearly affects wait IDD; measured with PLL and LVI enabled.

5.Stop IDD measured with PLL and LVI disengaged, OCS1 grounded, no port pins sourcing current. It is measured through combination of VDD, VDDAD, and VDDA.

6.The low-voltage inhibit reset is software selectable. Refer to Chapter 9 Low-Voltage Inhibit (LVI).

7.Maximum is highest voltage that POR is guaranteed.

8.If minimum VDD is not reached before the internal POR is released, RST must be driven low externally until minimum VDD is reached.

9.Maximum is highest voltage that POR is possible.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

Freescale Semiconductor 267