MC68HC908MR32 MC68HC908MR16
Page
 MC68HC908MR32 MC68HC908MR16
Data Sheet
MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev
 Date Revision Description Level Numbers
Revision History
Revision History
 List of Chapters
 List of Chapters MC68HC908MR32 MC68HC908MR16 Data Sheet, Rev
 Table of Contents
 Chapter Clock Generator Module CGM
Table of Contents
Chapter Analog-to-Digital Converter ADC
 Chapter Configuration Register Config
Chapter Computer Operating Properly COP
 Chapter Low-Voltage Inhibit LVI
Chapter Central Processor Unit CPU
Chapter External Interrupt IRQ
 Chapter Pulse-Width Modulator for Motor Control Pwmmc
Chapter Power-On Reset POR
Chapter Input/Output I/O Ports Ports
 Chapter Serial Communications Interface Module SCI
 Chapter System Integration Module SIM
Chapter Serial Peripheral Interface Module SPI
 Chapter Timer Interface a Tima
 Chapter Timer Interface B Timb
Chapter Development Support
 Chapter Electrical Specifications
Chapter Ordering Information and Mechanical Specifications
 Introduction
Features
Chapter General Description
 MCU Block Diagram
General Description
 Diagram
MCU Block
 Pin Assignments
Pin QFP Pin Assignments
 Pin Sdip Pin Assignments
Pin Assignments
 External Reset Pin RST
Power Supply Pins VDD and VSS
Oscillator Pins OSC1 and OSC2
CGM Power Supply Pins Vdda and Vssad
 Port B I/O Pins PTB7/ATD7-PTB0/ATD0
Analog Power Supply Pins Vddad and Vssad
Port a Input/Output I/O Pins PTA7-PTA0
Port C I/O Pins PTC6-PTC2 and PTC1/ATD9-PTC0/ATD8
 Port F I/O Pins PTF5/TxD-PTF4/RxD and PTF3/MISO-PTF0/SPSCK
PWM Ground Pin Pwmgnd
 Reserved Memory Locations
Chapter Memory
Unimplemented Memory Locations
 Memory
I/O Section
Memory Map
 MC68HC908MR32 Memory Map
Memory Map
 Control, Status, and Data Registers Summary Sheet 1
Memory Addr
 Control, Status, and Data Registers Summary Sheet 2
Memory Map Addr Register Name Bit
 Control, Status, and Data Registers Summary Sheet 3
Memory Addr Register Name
 Control, Status, and Data Registers Summary Sheet 4
 Control, Status, and Data Registers Summary Sheet 5
Memory Addr Register Name Bit
 Control, Status, and Data Registers Summary Sheet 6
Addr Register Name
 Control, Status, and Data Registers Summary Sheet 7
 Control, Status, and Data Registers Summary Sheet 8
 Vector Addresses
Address Vector Low
 Monitor ROM
Random-Access Memory RAM
Monitor ROM
Address Vector
 Flash Memory Flash
Flash Control Register
 Mass Mass Erase Control Bit
Hven High-Voltage Enable Bit
Flash Page Erase Operation
Erase Erase Control Bit
 Flash Mass Erase Operation
 Flash Program Operation
Only bytes which are currently $FF may be programmed
 Flash Programming Flowchart
 Flash Block Protection
Flash Block Protect Register
 Examples of Protect Start Address
Wait Mode
Stop Mode
 Chapter Analog-to-Digital Converter ADC
Functional Description
 Block Diagram Highlighting ADC Block and Pins
Analog-to-Digital Converter ADC
 Functional Description
ADC Port I/O Pins
Voltage Conversion
 Result Justification
Conversion Time
Continuous Conversion
 Bit Truncation Mode Error
Monotonicity
 Interrupts
Wait Mode
I/O Signals
 ADC External Connections
I/O Registers
ADC Voltage In Advin
6.2 ANx
 Aien ADC Interrupt Enable Bit
ADC Status and Control Register
 Mux Channel Select
Input Select
 ADC Data Register High
ADC Data Register Low
 ADC Clock Rate
ADC Clock Register
ADC Clock Divide Ratio
 Analog-to-Digital Converter ADC
 Chapter Clock Generator Module CGM
Cgmvclk
 CGM Block Diagram
Clock Generator Module CGM
 PLL Circuits
Phase-Locked Loop Circuit PLL
Crystal Oscillator Circuit
 Acquisition and Tracking Modes
Manual and Automatic PLL Bandwidth Modes
 Variable Definition
Programming the PLL
Variable Definitions
 Base Clock Selector Circuit
Special Programming Exceptions
 CGM External Connections
CGM External Connections
 Crystal Amplifier Input Pin OSC1
PLL Analog Power Pin Vdda
Oscillator Enable Signal Simoscen
Crystal Amplifier Output Pin OSC2
 CGM Base Clock Output Cgmout
Crystal Output Frequency Signal Cgmxclk
CGM Registers
CGM CPU Interrupt Cgmint
 Pllon PLL On Bit
PLL Control Register
Pllf PLL Interrupt Flag
BCS Base Clock Select Bit
 PLL Bandwidth Control Register
Lock Lock Indicator Bit
ACQ Acquisition Mode Bit
PCTL30 Unimplemented Bits
 PBWC30 Reserved for Test
PLL Programming Register
XLD Crystal Loss Detect Bit
VCO Frequency Multiplier N Selection
 VRS74 VCO Range Select Bits
Interrupts
 Parametric Influences on Reaction Time
Acquisition/Lock Time Specifications
Acquisition/Lock Time Definitions
 Reaction Time Calculation
Acquisition/Lock Time Specifications
Choosing a Filter Capacitor
 Frequency
 Chapter Configuration Register Config
 Configuration Register
 COP Block Diagram
Chapter Computer Operating Properly COP
 Reset Vector Fetch
Power-On Reset
Internal Reset
Copctl Write
 Copd COP Disable
Monitor Mode
Stop Mode
COP Control Register
 Freescale Semiconductor
 Chapter Central Processor Unit CPU
CPU Registers
 Central Processor Unit CPU
Accumulator
Index Register
 CPU Registers
Stack Pointer
Program Counter
 Interrupt Mask
Condition Code Register
Half-Carry Flag
Negative Flag
 CPU During Break Interrupts
Low-Power Modes
Arithmetic/Logic Unit ALU
Zero Flag
 Instruction Set Summary
Instruction Set Summary Sheet 1
 Source Operation Description On CCR Form
Instruction Set Summary Sheet 2
Instruction Set Summary
 Instruction Set Summary Sheet 3
Dbnz opr,rel
 Instruction Set Summary Sheet 4
JMP ,X
 Instruction Set Summary Sheet 5
Operation Description On CCR Form
 Opcode Map
Opcode Map
Instruction Set Summary Sheet 6
 Opcode Map
9ED 9EE
 IRQ Module Block Diagram
Chapter External Interrupt IRQ
 IRQ Pin
External Interrupt IRQ
 IRQ Interrupt Flowchart
IRQ Pin
 IRQ Status and Control Register
IRQ Status and Control Register Iscr
 Irqf IRQ Flag
IRQ Status and Control Register
 Freescale Semiconductor
 LVI Module Block Diagram
Chapter Low-Voltage Inhibit LVI
 Polled LVI Operation
Forced Reset Operation
False Reset Protection
LVI Trip Selection
 Lviout Bit Indication
LVI Status and Control Register
LVI Interrupts
LVI Status and Control Register
 100 Freescale Semiconductor
 Chapter Input/Output I/O Ports Ports
I/O Port Register Summary
 Input/Output I/O Ports Ports Addr Register Name
 Data Direction Register a
Port a
Port a Data Register
Port a
 Port a Pin Functions
Port B
Port B Data Register
Input/Output I/O Ports Ports
 Port B
Data Direction Register B
Port B Pin Functions
 Data Direction Register C
Port C
Port C Data Register
 Port D
Port D
Port C Pin Functions
PTC60
 Port E Data Register
PTD Bit Pin Mode Accesses to PTD Read
Port E
Port D Pin Functions
 Port E Pin Functions
Ddre Bit PTE Bit Pin Mode Accesses to Ddre Accesses to PTE
Data Direction Register E
Port E
 Data Direction Register F
Port F
Port F Data Register
 Port F Pin Functions
Port F
 112 Freescale Semiconductor
 Chapter Power-On Reset POR
 114 Freescale Semiconductor
 Chapter Pulse-Width Modulator for Motor Control Pwmmc
 Block Diagram Highlighting Pwmmc Block and Pins
Pulse-Width Modulator for Motor Control Pwmmc
 PWM Module Block Diagram
Features
 Register Summary Sheet 2
 Features Addr Register Name Bit
Register Summary Sheet 3
 Resolution
Timebase
 Edge-Aligned PWM Positive Polarity
Timebase
 Load Operation
PWM Generators
Prescaler
PWM Prescaler
 Reload Frequency Change
PWM Interrupt Requests
 Center-Aligned PWM Value Loading
 PWMVALxHPWMVALxL Condition PWM Value Used
PWM Data Overflow and Underflow Conditions
PWM Data Overflow and Underflow Conditions
 12. Complementary Pairing
Output Control
 Dead-Time Insertion
Output Control
 14. Dead-Time Generators
 15. Effects of Dead-Time Insertion
 17. Dead-Time and Small Pulse Widths
 Current Sense Pins
Current Voltage On Current
 Correction Methods
Current Correction Bits Correction Method ISENS1 and ISENS0
 Output Polarity
20. Top/Bottom Correction for PWMs 1
 21. PWM Polarity
 OUTx Bits
OUTx Bit Complementary Mode Independent Mode
PWM Output Port Control
 23. Dead-Time Insertion During Outctl =
 Fault Protection
Fault Protection
Fault Condition Input Pins
 26. PWM Disabling Scheme
 Fault Pin Filter
Automatic Mode
 28. PWM Disabling in Automatic Mode
Manual Mode
 Software Output Disable
Output Port Control
 32. Pwmen and PWM Pins
Initialization and the Pwmen Bit
 Control Logic Block
PWM Operation in Wait Mode
PWM Operation in Wait Mode
PWM Counter Registers
 PWM Counter Modulo Registers
35. PWM Counter Modulo Register High Pmodh
 PWMx Value Registers
Control Logic Block
 PWM Control Register
Disy Software Disable Bit for Bank Y Bit
Pwmint PWM Interrupt Enable Bit
Pwmf PWM Reload Flag
 Pwmen PWM Module Enable Bit
LDOK- Load OK Bit
 IPOL1 Top/Bottom Correction Bit for PWM Pair 1 PWMs 1
 PRSC1 and PRSC0 PWM Prescaler Bits
IPOL2 Top/Bottom Correction Bit for PWM Pair 2 PWMs 3
IPOL3 Top/Bottom Correction Bit for PWM Pair 3 PWMs 5
 Dead-Time Write-Once Register
PWM Disable Mapping Write-Once Register
Fault Control Register
 FINT1 Fault 1 Interrupt Enable Bit
FINT3 Fault 3 Interrupt Enable Bit
FINT2 Fault 2 Interrupt Enable Bit
 Fault Status Register
 Fault Acknowledge Register
 DT1 Dead-Time 1 Bit
PWM Output Control Register
DT2 Dead-Time 2 Bit
10. OUTx Bits
 PWM Glossary
PWM Glossary
 48. PWM Load Cycle/Frequency Definition
 Chapter Serial Communications Interface Module SCI
 Block Diagram Highlighting SCI Block and Pins
Serial Communications Interface Module SCI
 SCI Module Block Diagram
 Data Format
Serial Communications Interface Module SCI Addr
 Transmitter
SCI Transmitter
 Break Characters
Character Length
Character Transmission
 Inversion of Transmitted Output
Receiver
Idle Characters
Transmitter Interrupts
 SCI Receiver Block Diagram
 Character Reception
Data Sampling
 Start Bit Verification
Data Bit Recovery
Stop Bit Recovery
 Receiver Wakeup
Framing Errors
Error Interrupts
Receiver Interrupts
 13.6.1 PTF5/TxD Transmit Data
13.6 I/O Signals
SCI During Break Module Interrupts
 SCI Control Register
13.7 I/O Registers
13.6.2 PTF4/RxD Receive Data
 PEN Parity Enable Bit
Ensci Enable SCI Bit
Mode Character Length Bit
Txinv Transmit Inversion Bit
 Control Bits Character Format
Tcie Transmission Complete Interrupt Enable Bit
Character Format Selection
Start Data Parity Stop
 TE Transmitter Enable Bit
Scrie SCI Receive Interrupt Enable Bit
Ilie Idle Line Interrupt Enable Bit
RE Receiver Enable Bit
 Feie Receiver Framing Error Interrupt Enable Bit
Orie Receiver Overrun Interrupt Enable Bit
Neie Receiver Noise Error Interrupt Enable Bit
Peie Receiver Parity Error Interrupt Enable Bit
 Scrf SCI Receiver Full Bit
SCI Status Register
TC Transmission Complete Bit
 Idle Receiver Idle Bit
Or Receiver Overrun Bit
 NF Receiver Noise Flag Bit
FE Receiver Framing Error Bit
PE Receiver Parity Error Bit
 RPF -Reception-in-Progress Flag
SCI Data Register
SCI Baud Rate Register
SCI Baud Rate Prescaling
 SCI Baud Rate Selection
Baud Rate Divisor BD
 SCI Baud Rate Selection Examples
Baud Rate Divisor PD Divisor BD
 180 Freescale Semiconductor
 Chapter System Integration Module SIM
Signal Name Conventions
Signal Name Description
 Bus Timing
Clock Startup from POR or LVI Reset
SIM Bus Clock Control and Generation
System Integration Module SIM
 External Pin Reset
Reset and System Initialization
Clocks in Wait Mode
Reset and System Initialization
 PIN Bit Set Timing
Active Resets from Internal Sources
Reset Type Number of Cycles Required to Set PIN
 Power-On Reset POR
Computer Operating Properly COP Reset
 SIM Counter
SIM Counter During Power-On Reset
SIM Counter and Reset States
 Exception Control
Exception Control
Interrupts
 Interrupt Processing
 Interrupt Recovery
Hardware Interrupts
 Software Interrupt SWI Instruction
Low-Power Mode
Reset
 SIM Registers
SIM Registers
SIM Break Status Register
 Ilop Illegal Opcode Reset Bit
SIM Reset Status Register
PIN External Reset Bit
Ilad Illegal Address Reset Bit opcode fetches only
 SIM Break Flag Control Register
 194 Freescale Semiconductor
 Pin Name Conventions
Chapter Serial Peripheral Interface Module SPI
Pin Name Conventions
 Block Diagram Highlighting SPI Block and Pins
Serial Peripheral Interface Module SPI
 SPI Module Block Diagram
 Master Mode
Serial Peripheral Interface Module SPI Addr
 Transmission Formats
Slave Mode
Clock Phase and Polarity Controls
Transmission Formats
 Transmission Format When Cpha =
Transmission Format Cpha =
 Transmission Initiation Latency
 Transmission Start Delay Master
 Error Conditions
Error Conditions
Overflow Error
 Mode Fault Error
10. Clearing Sprf When Ovrf Interrupt Is Not Enabled
 Freescale Semiconductor 205
 SPI Interrupts
Flag Request
 Queuing Transmission Data
Resetting the SPI
Resetting the SPI
 15.11 I/O Signals
12. SPRF/SPTE CPU Interrupt Timing
 Mosi Master Out/Slave
Signals
Miso Master In/Slave Out
Spsck Serial Clock
 15.12 I/O Registers
SPI Configuration
SPI Configuration State of SS Logic
VSS Clock Ground
 Spmstr SPI Master Bit
Cpha Clock Phase Bit
Spwom SPI Wired-OR Mode Bit
Cpol Clock Polarity Bit
 Errie Error Interrupt Enable Bit
SPE SPI Enable Bit
SPTIE- SPI Transmit Interrupt Enable Bit
SPI Status and Control Register
 Ovrf Overflow Bit
Modf Mode Fault Bit
Modfen Mode Fault Enable Bit
Spte SPI Transmitter Empty Bit
 SPI Data Register
SPI Master Baud Rate Selection
 Chapter Timer Interface a Tima
2is a block diagram of the Tima
 Block Diagram Highlighting Tima Block and Pins
Timer Interface a Tima
 Tima Block Diagram
 Timer Interface a Tima Addr Register Name Bit
TIM I/O Register Summary
 Tima Counter Prescaler
Input Capture
 Output Compare
Unbuffered Output Compare
 Pulse-Width Modulation PWM
Buffered Output Compare
 Unbuffered PWM Signal Generation
PWM Period and Pulse Width
 Buffered PWM Signal Generation
PWM Initialization
 224 Freescale Semiconductor
 16.7 I/O Registers
16.6 I/O Signals
Tima Channel I/O Pins PTE4/TCH0A-PTE7/TCH3A
Tima Clock Pin PTE3/TCLKA
 Tstop Tima Stop Bit
Toie Tima Overflow Interrupt Enable Bit
Trst Tima Reset Bit
 Prescaler Selection
Tima Counter Registers
PS20 Prescaler Select Bits
PS20 Tima Clock Source
 Tima Counter Modulo Registers
Tima Channel Status and Control Registers
 CHxIE Channel x Interrupt Enable Bit
 ELSxB and ELSxA Edge/Level Select Bits
MSxB Mode Select Bit B
MSxA Mode Select Bit a
 TOVx Toggle-On-Overflow Bit
MSxBMSxA ELSxBELSxA Mode Configuration
Mode, Edge, and Level Selection
CHxMAX Channel x Maximum Duty Cycle Bit
 Tima Channel Registers
10. Tima Channel Registers
 10. Tima Channel Registers TACH0H/L-TACH3H/L
 234 Freescale Semiconductor
 Chapter Timer Interface B Timb
Timb module is not available in the 56-pin Sdip
 Block Diagram Highlighting Timb Block and Pins
Timer Interface B Timb
 Timb Block Diagram
 Timer Interface B Timb Addr Register Name Bit
Timb Counter Prescaler
 Freescale Semiconductor 239
 240 Freescale Semiconductor
 Freescale Semiconductor 241
 242 Freescale Semiconductor
 Timb Clock Pin PTE0/TCLKB
17.6 I/O Signals
Timb Channel I/O Pins PTE1/TCH0B-PTE2/TCH1B
 Timb Status and Control Register
Toie Timb Overflow Interrupt Enable Bit
17.7 I/O Registers
 PS20 Timb Clock Source
Trst Timb Reset Bit
Tstop Timb Stop Bit
 Timb Counter Registers
Timb Counter Modulo Registers
 Timb Channel Status and Control Registers
 248 Freescale Semiconductor
 PWM
 Timb Channel Registers
10. Timb Channel Registers TBCH0H/L-TBCH1H/L
 Functional Description
Chapter Development Support
Break Module BRK
Flag Protection During Break Interrupts
 Break Module Block Diagram
Development Support
 Low-Power Modes
Break Module Registers
 Break Address Registers
Break Status and Control Register
Brka Break Active Bit
 Break Flag Control Register
Monitor ROM MON
Break Status Register
Monitor ROM MON
 Normal Monitor Mode
Entering Monitor Mode
Mode Differences
 Monitor Mode Circuit
 Monitor Mode Signal Requirements and Options
$FFFF
 Forced Monitor Mode
Data Format
 Echoing
Break Signal
Commands
 Iread Indexed Read Command
Read Read Memory Command
Write Write Memory Command
Command Sequence
 RUN Run User Program Command
Iwrite Indexed Write Command
Readsp Read Stack Pointer Command
 Monitor Baud Rate Selection
Security
Baud Rate
 13. Monitor Mode Entry Timing
 Absolute Maximum Ratings
Chapter Electrical Specifications
Characteristic1 Symbol Value Unit
 Characteristic Symbol Value Unit
Thermal Characteristics
Electrical Specifications
Functional Operating Range
 Characteristic1 Symbol Min Typ2 Max Unit
DC Electrical Characteristics
DC Electrical Characteristics
 Characteristic Symbol Min Max Unit
Flash Memory Characteristics
Characteristic Symbol Min Typ Max Unit
Control Timing
 Diagram Characteristic2 Symbol Min Max Unit Number1
Serial Peripheral Interface Characteristics
Serial Peripheral Interface Characteristics
 SPI Master Timing
 SPI Slave Timing
 Characteristic Symbol Min Typ Max
TImer Interface Module Characteristics
Clock Generation Module Component Specifications
CGM Operating Conditions
 Description Symbol Min Typ Max
CGM Acquisition/Lock Time Specifications
CGM Acquisition/Lock Time Specifications
 Analog-to-Digital Converter ADC Characteristics
3FF
 Order Numbers
Chapter Ordering Information and Mechanical Specifications
Order Numbers
MC Order Number Operating
 Ordering Information and Mechanical Specifications
20.3 64-Pin Plastic Quad Flat Pack QFP
 20.4 56-Pin Shrink Dual In-Line Package Sdip
Pin Shrink Dual In-Line Package Sdip
 278 Freescale Semiconductor
 Appendix a MC68HC908MR16
 Figure A-1. MC68HC908MR16 Memory Map
MC68HC908MR16
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