Freescale Semiconductor MC68HC908MR16, MC68HC908MR32 Serial Peripheral Interface Characteristics

Serial Peripheral Interface Characteristics

19.8 Serial Peripheral Interface Characteristics

Diagram	Characteristic(2)	Symbol	Min	Max	Unit
Number(1)
	Operating frequency	fOP(M)	fOP/128	fOP/2
	Master				MHz
	Slave	fOP(S)	dc	fOP
	Cycle time	tCYC(M)			tCYC
1	Master		2	128
	Slave	tCYC(S)	1	—
2	Enable lead time	tLead(S)	15	—	ns
3	Enable lag time	tLag(S)	15	—	ns
	Clock (SPCK) high time	tSCKH(M)
4	Master		100	—	ns
	Slave	tSCKH(S)	50	—
	Clock (SPCK) low time	tSCKL(M)
5	Master		100	—	ns
	Slave	tSCKL(S)	50	—
	Data setup time (inputs)	tSU(M)	45	—
6	Master				ns
		tSU(S)	5	—
	Slave
	Data hold time (inputs)	tH(M)	0	—
7	Master				ns
		tH(S)	15	—
	Slave
8	Access time, slave(3)	tA(CP0)	0	40	ns
	CPHA = 0
		tA(CP1)	0	20
	CHPA = 1
9	Disable time, slave(4)	tDIS(S)	—	25	ns
	Data valid time after enable edge
10	Master	tV(M)	—	10	ns
	Slave(5)	tV(S)	—	40

1.VDD = 5.0 Vdc ± 10%, all timing is shown with respect to 20% VDD and 70% VDD, unless otherwise noted; assumes 100 pF load on all SPI pins

2.Numbers refer to dimensions in Figure 19-1and Figure 19-2.

3.Time to data active from high-impedance state

4.Hold time to high-impedance state

5.With 100 pF on all SPI pins

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

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