Freescale Semiconductor MC68HC908MR32, MC68HC908MR16 manual PWM Reload Frequency

Pulse-Width Modulator for Motor Control (PWMMC)

12.9.5 PWM Control Register 2

PWM control register 2 (PCTL2) controls the PWM load frequency, the PWM correction method, and the PWM counter prescaler. For ease of software and to avoid erroneous PWM periods, some of these register bits are buffered. The PWM generator will not use the prescaler value until the LDOK bit has been set, and a new PWM cycle is starting. The correction bits are used at the beginning of each PWM cycle (if the ISENSx bits are configured for software correction). The load frequency bits are not used until the current load cycle is complete.

See Figure 12-40.

NOTE

The user should initialize this register before enabling the PWM.

Address:

Read:

Write:

Reset:

$0021
Bit 7	6	5	4	3	2	1	Bit 0
LDFQ1	LDFQ0	0	IPOL1	IPOL2	IPOL3	PRSC1	PRSC0
0	0	0	0	0	0	0	0
	= Unimplemented		Bold	= Buffered

Figure 12-40. PWM Control Register 2 (PCTL2)

LDFQ1 and LDFQ0 — PWM Load Frequency Bits

These buffered read/write bits select the PWM CPU load frequency according to Table 12-8.

NOTE

When reading these bits, the value read is the buffer value (not necessarily the value the PWM generator is currently using).

The LDFQx bits take effect when the current load cycle is complete regardless of the state of the load okay bit, LDOK.

Table 12-8. PWM Reload Frequency

Reload Frequency Bits	PWM Reload Frequency
LDFQ1 and LDFQ0
00	Every PWM cycle
01	Every 2 PWM cycles
10	Every 4 PWM cycles
11	Every 8 PWM cycles

NOTE

Reading the LPFQx bit reads the buffered values and not necessarily the values currently in effect.

IPOL1 — Top/Bottom Correction Bit for PWM Pair 1 (PWMs 1 and 2)

This buffered read/write bit selects which PWM value register is used if top/bottom correction is to be achieved without current sensing.

1 = Use PWM value register 2.

0 = Use PWM value register 1.

MC68HC908MR32 • MC68HC908MR16 Data Sheet, Rev. 6.1

148 Freescale Semiconductor