Intel® PXA27x Processor Family Power Requirements
The processor commands entry into sleep mode by de-asserting PWR_EN to the PMIC once the PMIC and system are prepared. The PMIC responds by turning off the specified set of supplies along with VCC_CORE, VCC_PLL, and VCC_SRAM. For entry into sleep mode, there is no requirement for how long these supplies require to shut down after de-assertion of PWR_EN. (However, for entry into deep-sleep mode, these supplies must shut down before the de-assertion of SYS_EN to ensure that supply sequencing requirements are met.)
A wakeup event must occur to exit sleep mode. For example, the wakeup event can be a transition on one of the wakeup-capable GPIOs that has been programmed to respond to a level change, or it can be an interrupt from a timer in the real-time clock unit. In response, the PXA27x processor asserts PWR_EN to the PMIC and starts its PWR_DEL timer. The PMIC turns on all of its low- voltage supplies (VCC_CORE, VCC_SRAM, and VCC_PLL) and when all supplies are stable and within regulation, the PMIC de-asserts nVDD_FAULT. The PXA27x processor returns the system to sleep mode if nVDD_FAULT is not de-asserted before the PWR_DEL timer expires. Otherwise the PXA27x processor completes the sleep-reset boot sequence. See the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification data sheet for entry and exit sleep-mode timings.
Note: Upon exiting from sleep mode, the processor returns to the last clock frequency prior to sleep mode entry. Likewise, the PMIC must also be able to return to the previous voltage level prior to entering sleep mode. It is necessary for the PMIC to accommodate the appropriate voltage level upon exiting. All wake-up events are ignored until nBATT_FAULT is de-asserted if the nBATT_FAULT signal asserts in sleep or deep sleep.
5.2.2Deep Sleep Entry and Exit
The PXA27x processor prepares the PMIC for deep sleep prior to entering deep sleep by specifying which additional system regulators are to be disabled or shut down when the PXA27x processor commands deep-sleep entry. The PXA27x processor controls deep-sleep entry by de- assertion of the SYS_EN signal. The set of regulators to be turned off can be fixed in PMIC hardware or it can be programmable. If programmable, a register in the PMIC is loaded via I2C to specify which regulators turn off. The regulators for VCC_IO, VCC_LCD, VCC_MEM, VCC_BB, VCC_USB, and VCC_USIM are enabled and disabled using SYS_EN, but other regulators in the system may or may not need to be enabled/disabled, depending upon system design.
The PXA27x processor places DRAM memory into self-refresh mode before entering deep sleep. In self-refresh mode, the DRAM must still be powered, but power decreases substantially. Alternatively, if DRAM contents do not need to be preserved, the PXA27x processor can place the DRAMs into deep-power-down mode. Doing so reduces DRAM power to microamps, even though voltage from the PMIC is still maintained on the DRAM power signals.
Note: The PXA271 and PXA272 processors contain stacked memory which is supplied power via the VCC_MEM power domain.
The PXA27x processor commands entry into deep-sleep mode by de-asserting PWR_EN once the PMIC and system are prepared. The PMIC responds by turning off the set of low-voltage power supplies designated either by the prior register setting, or fixed in PMIC hardware. After a delay to allow the low-voltage supplies to shut down, the PXA27x processor de-asserts SYS_EN to the PMIC, and the PMIC responds by turning off the necessary combination of high-voltage supplies. Note that all power-supply sequencing requirements must be observed: low-voltage supplies must power down before any high-voltage supplies power down. See the Intel® PXA27x Processor Family Electrical, Mechanical, and Thermal Specification data sheet for entry and exit deep-sleep mode timings.
