Appendix C: POST Code Diagnostic LED DecoderIntel® Server Boards S5000PSL and S5000XSL TPS
In the below example, BIOS sends a value of ACh to the diagnostic LED decoder. The LEDs are decoded as follows:
Red bits = 1010b = Ah
Green bits = 1100b = Ch
Since the red bits correspond to the upper nibble and the green bits correspond to the lower nibble, the two are concatenated as ACh.
Table 47. POST Progress Code LED Example
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| 8h |
| 4h |
| 2h |
| 1h | ||||
LEDs | Red |
| Green | Red |
| Green | Red |
| Green | Red |
| Green |
ACh | 1 |
| 1 | 0 |
| 1 | 1 |
| 0 | 0 |
| 0 |
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Result | Amber |
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| Green |
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| Red |
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| Off |
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| MSB | Bit 2 |
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| Bit 1 |
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| LSB | ||
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| Checkpoint | Diagnostic LED Decoder | Description | |||||
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| G=Green, R=Red, A=Amber |
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| MSB | Bit 2 | Bit 1 | LSB |
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| Host Processor |
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| 0x10h | Off | Off | Off | R | |||
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| 0x11h | Off | Off | Off | A | Host processor cache initialization (including AP) | ||
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| 0x12h | Off | Off | G | R | Starting application processor initialization | ||
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| 0x13h | Off | Off | G | A | SMM initialization | ||
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| Chipset |
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| 0x21h | Off | Off | R | G | Initializing a chipset component | ||
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| Memory |
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| 0x22h | Off | Off | A | Off | Reading configuration data from memory (SPD on DIMM) | ||
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| 0x23h | Off | Off | A | G | Detecting presence of memory | ||
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| 0x24h | Off | G | R | Off | Programming timing parameters in the memory controller | ||
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| 0x25h | Off | G | R | G | Configuring memory parameters in the memory controller | ||
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| 0x26h | Off | G | A | Off | Optimizing memory controller settings | ||
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| 0x27h | Off | G | A | G | Initializing memory, such as ECC init | ||
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| 0x28h | G | Off | R | Off | Testing memory | ||
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| PCI Bus |
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| 0x50h | Off | R | Off | R | Enumerating PCI busses | ||
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| 0x51h | Off | R | Off | A | Allocating resources to PCI busses | ||
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| 0x52h | Off | R | G | R | Hot Plug PCI controller initialization | ||
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| 0x53h | Off | R | G | A | Reserved for PCI bus | ||
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| 0x54h | Off | A | Off | R | Reserved for PCI bus | ||
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| 0x55h | Off | A | Off | A | Reserved for PCI bus | ||
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| 0x56h | Off | A | G | R | Reserved for PCI bus | ||
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110 |
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| Revision 1.2 | |||
Intel order number: