Intel® Server Boards S5000PSL and S5000XSL TPS | List of Tables |
To boot the system, the system BIOS on the server board uses a dedicated I2C bus to retrieve DIMM information needed to program the MCH memory registers. The following table provides the I2C addresses for each DIMM socket.
Table 3. I2C Addresses for Memory Module SMB
Device | Address |
DIMM A1 | 0xA0 |
|
|
DIMM A2 | 0xA2 |
|
|
DIMM B1 | 0xA0 |
|
|
DIMM B2 | 0xA2 |
|
|
DIMM C1 | 0xA0 |
|
|
DIMM C2 | 0xA2 |
|
|
DIMM D1 | 0xA0 |
|
|
DIMM D2 | 0xA2 |
|
|
The MCH supports several memory RASUM (Reliability, Availability, Serviceability, Usability, and Manageability) features. These features include the Intel® x4 Single Device Data Correction (Intel® x4 SDDC) for the following:
Memory error detection and correction
Memory scrubbing
Retry on correctable errors
Memory
DIMM sparing
Memory mirroring
See the Intel® S5000 Server Board Family Datasheet for more information about these features.
Revision 1.2 | 33 |
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