Server Board Overview | Intel® Server Boards S5000PSL and S5000XSL TPS |
3.1.3Memory Sub-system
The MCH masters four fully buffered DIMM (FBD) memory channels. FBD memory utilizes a narrow high speed frame oriented interface referred to as a channel. The four FBD channels are organized into two branches of two channels per branch. Each branch is supported by a separate memory controller. The two channels on each branch operate in
On the Intel® Server Boards S5000PSL and S5000XSL, a pair of channels becomes a branch where Branch 0 consists of channels A and B, and Branch 1 consists of channels C and D. FBD memory channels are organized into two branches for support of RAID 1 (mirroring).
MCH
Branch 0
Branch 1
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Channel A |
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A1 |
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DIMM | A2 |
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DIMM | B2 |
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| DIMM | D2 |
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| DIMM |
TP02299
Figure 12. Memory Layout
32 | Revision 1.2 |
| Intel order number: |