Intel® Server Board Set SE8500HW4

Intel® Server Board Set SE8500HW4 Memory Board

4.4Data Correction and Scrubbing

The XMB employs a Single Device Data Correction (x8 SDDC) algorithm for the memory subsystem that will recover from a component failure during read and write transactions. This corrects and logs a correctable memory error, and logs uncorrectable memory errors.

A patrol scrub can be turned on in the system BIOS that scrubs roughly 64GB of memory behind each XMB every day. The patrol scrub confirms the data for one cache line every 16k core cycles and then increments the address one cache line. During patrol scrub, an erroneous read will be logged and re-read. If the re-read is correctable, it is corrected (scrubbed) in memory. A conflicting read or write request pending issue will be held until the scrub is finished.

4.5Memory Board Components

 

 

 

 

 

 

DIMM_1B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIMM_1A

 

 

 

 

 

 

 

Remote

 

 

 

 

 

 

 

 

 

 

 

Temperature

 

 

 

 

 

 

 

 

Temperature

 

 

 

 

 

 

 

 

 

 

 

Sensor

Sensor

 

 

 

 

DIMM_2B

 

 

 

 

 

Controller

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DIMM_2A

 

 

 

 

 

 

 

 

 

 

 

Channel A

 

 

 

Channel B

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

E8500 eXtended Memory

 

 

 

 

 

 

 

 

 

 

 

Bridge

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

IMI

 

I2C

 

 

 

 

 

 

 

 

 

 

FRU

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Main Board Connector

Figure 6. Memory Board Block Diagram

Revision 1.0

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