Intel® Server Board Set SE8500HW4

Electrical Specifications

 

Table 36. Reset Types

 

 

Reset Type

Description

 

 

Front Panel Power Button

De-asserts PS_ON_L to the power supply and causes the system to shut down.

 

 

FP_RST_BTN_N

These signals are connected to the “Sources of Reset” logic inside the PLD. Any

ITP_RST

time any one of these signals is transitions LOW, the output of the logic

SYS_ICH_RST asserts the SYS_RST_N to ICH5. Upon which ICH5 asserts

 

 

PCI_RST_N back to PLD. Then PLD asserts the RESET# input to NB, PXH and

 

Intel® IOP332 Storage I/O Processor.

 

 

NB_RST

This signal is controlled through the BIOS in ICH5.

 

 

8.4Interrupts

The Intel® E8500 Chipset supports both XAPIC and 8259 interrupt delivery mechanisms. IOxAPIC controllers are located in the PXH, Intel® IOP332 Storage I/O Processor, and the ICH5. The 8259 controller is located in the ICH5. Figure 17 illustrates the interrupt routing in the Intel® Server Board Set SE8500HW4.

Figure 17. Interrupt Block Diagram

Revision 1.0

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Intel order number D22893-001