Intel® Server Board Set SE8500HW4 | System BIOS |
10.3.1.4Microcode Update API
Recent Intel processors have the capability of correcting specific errata through the loading of an
10.3.1.5Intel® Hyper-Threading Technology
The BIOS will create additional entries in the ACPI MP tables to describe the virtual processors. The SMBIOS Type 4 structure will only show the physical processors installed. It will not describe the virtual processors.
Because some operating systems are not able to efficiently utilize the Intel®
10.3.1.6Intel® SpeedStep® Technology
10.3.1.7Intel® Extended Memory 64 Technology
The Intel® Server Board Set SE8500HW4 BIOS supports Intel® Extended Memory 64 Technology (EM64T) for executing both
10.3.2Memory
ECC memory must be initialized by the BIOS before it can be used. The BIOS executes a hardware memory test before configuring memory during POST and during runtime when a Memory Board is hot inserted to the system. The memory test can be enabled or disabled based on a BIOS setup option. During POST the hardware memory test is executed in parallel on all Memory Boards before video is available. Hardware memory testing tests every byte of memory location and cannot be stopped once initiated. The hardware isolates an uncorrectable error down to a DIMM pair and a correctable error to a DIMM.
When the memory initialization test encounters bad DIMM(s), it disables the bad DIMM(s) and turns on the corresponding DIMM error LED indicator on the Memory Board. The BIOS also reports the correctable or uncorrectable error on the bad DIMM(s) and that the bad DIMM and its bank partner DIMM has disabled. If bad DIMM(s) from the memory test results in the BIOS
Revision 1.0 | 75 |
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