Intel® Server Board Set SE8500HW4

System BIOS

10.2 Rolling BIOS

The Intel® Server Board Set SE8500HW4 BIOS can be updated while the server is online, as opposed to immediately turning off the server after a BIOS update. This rolling BIOS features is supported by having two copies of the BIOS, the one in use, and a secondary copy, to which an updated BIOS version can be written. When ready, the system can roll forward to the new BIOS. In case of a failure with the new version, the system can roll back to the previous version. The Intel® Server Board Set SE8500HW4 does not automatically use the new BIOS, a reboot must happen to move to the new BIOS.

The Firmware Hub (BIOS flash) is divided into two partitions: primary and secondary. The active partition from which the system boots shall be referred to as the primary partition. The BIOS updates are written to the secondary partition. After the update, a notification flag will is set, and after subsequent boot following the BIOS update, the system will boot from the new primary BIOS partition. If the new BIOS fails to boot, specialized hardware will switch back to the BIOS on the other partition, thus affecting a “Roll Back”. BMC logs events associated with the BIOS updates to the SEL.

10.3 Initialization

10.3.1Processors

The Intel® Server Board Set SE8500HW4 has two processor front-side buses, each accommodating two processors. At reset, hardware arbitration will choose one BSP per FSB. However, the BIOS POST code requires only one processor for execution. This requires the BIOS to elect a “system BSP” using registers in the NB. The BIOS cannot guarantee which processor will be the system BSP, only that a system BSP will be selected. From this point forward, the system BSP will be referred to as just the BSP.

The BSP is responsible for executing the BIOS power-on self-test (POST) and preparing the machine to boot the operating system. At boot time, the system is in virtual wire mode and the BSP alone is programmed to accept local interrupts (INTR driven by programmable interrupt controller) and non-maskable interrupt (NMI)).

As a part of the boot process, the BSP wakes each AP. When awakened, an AP programs its Memory Type Range Registers (MTRRs) to be identical to those of the BSP. All APs execute a halt instruction with their local interrupts disabled. If the BSP determines that an AP exists that is a lower-featured processor or that has a lower value returned by the CPUID function, the BSP will switch to the lowest-featured processor in the system. This algorithm is described in [IA32_BWG]. The System Management Mode (SMM) handler expects all processors to respond to a Server Management Interrupt (SMI).

See Section 5.4 for more information on the BIOS and BMC interaction during the initial fault resilient booting process.

An FRB3 failure is recorded automatically by the BMC while AP failures are logged to the SEL by the BIOS.

The BMC maintains failure history for each processor in nonvolatile storage. There are three possible states for each processor slot:

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Intel order number D22893-001