Intel SE8500HW4 8.3Reset, Revision, Electrical Specifications, Intel order number D22893-001, Figure 16. Reset Block Diagram, Intel® Server Board Set SE8500HW4

Electrical Specifications Intel® Server Board Set SE8500HW4

Table 35. Typical Power-Down Timings

Ref	Description	Max	Typical	Min
t1	Time from front-panel power button push, to BMC asserting the power button to the	1s	90ms	50ms
	chipset. BMC debounces the power button input for 50ms
t2	Time from BMC asserting power button to chipset, until chipset responds with	5s	4.5s	–
	SLP_S5_L. Dependent on chipset setup.
t3	Time from when SLP_S5_L is asserted, to when BMC deasserts PS_ON_L to	1s	160ms	50ms
	complete system power-off.
t4	Time from BMC deasserting D2D enable, to when it deasserts PS_ON_L to	–	100µs	0µs
	complete system power-off.

8.3Reset

Figure 16 and Table 36 illustrate the reset routing in the Intel® Server Board Set SE8500HW4.

ITP_CPU_RESET_N

NB_RESETI_N

	XDP1	ITP_DBR_RESET_N
					ICH5
	XDP2		__RESETIRNB_N	__RSTSYSICH5_N
					_RESETPCI_N
RESET BUTTON
							IMI<D:A>_RST_EN	_N
						PLD 3
Video					PLD 1

FP_RST_BTN_N

PCI_RST_BUFF1_N

VID_PCI_RST_N

BUFFER

N	SIOVID RST	NICSIORST
SIOLPC LRESET
LPC_FWH_LRESET_N
		PX2B_RST_N

FWH1	SIO
		RSTIDE N	NICRST N
FWH2
		PCI
				Network

Front Panel

Connector

NB

N_RST_D_IMI	N_RST_C_IMI	N_RST_A_IMI N_RST_B_IMI		Hotplug
				IMI
PLD 1
			RESETI_N
			PXH_
			PXH
IOP332 RESETI N

IOP332

	OR	PB1_RESET
		PB0_RESET
	GATE
			LEVEL			Proc1
			TRANSLATOR
						Proc2
	PB1_RESET_N
						Proc3
	PB0_RESET_N
						Proc4
	IMI_A_ISO_RST_N				IMI CONN 1
	IMI_B_ISO_RST_N
					IMI CONN 2
	IMI_C_ISO_RST_N
					IMI CONN 3
	IMI_D_ISO_RST_N
					IMI CONN 4
PS1_PWROK
PS2_PWROK
				Power
			Connector

Figure 16. Reset Block Diagram

60	Revision 1.0
	Intel order number D22893-001