Intel® Server Board Set SE8500HW4 | Electrical Specifications |
Table 34. Typical Power-Up Timings
Ref | Description | Max | Typical | Min |
t1 | Time from | 2s | 1s | 50ms |
| chipset. This includes the private store update for Pwr State change, which is on the |
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| order of 500ms + overhead, which accounts for other task completion time like Init |
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| Agent. BMC also debounces signal for 50ms. |
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t2 | Time from BMC asserting power button to chipset, until chipset responds with | – | 16ms | 60µs |
| SLP_S5. |
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t3 | Time from when SLP_S5 is asserted, to when BMC asserts PS_ON_L to complete | 1s | 97ms | 50ms |
| system |
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t4 | Time from when BMC has completed driving its | – | 500ms | 250ms |
| asserts power good back to BMC. |
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8.2.2Power-Down Sequence
POWER_SW_L
(I)
t1
SM_PWRBTN_L
(O)
t2
SLP_S5P_L
(I)
t3
PS_ON_L
(O)
SYS_PWROK | t4 |
| |
(I) |
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Figure 15. Typical Power-Down Sequence
Revision 1.0 | 59 |
| Intel order number |