Server Management | Intel® Server Board Set SE8500HW4 |
5.6.1Intelligent Platform Management Buses (IPMB)
The IPMB is a communication protocol that utilizes a 100 KB/s I2C bus. The IPMB implementation in the BMC is compliant with the IPMB v1.0, revision 1.0, with the BMC having an IPMB slave address of 0x20.
The BMC both sends and receives IPMB messages over the IPMB interface.
Table 14. Platform I2C Buses
Physical | Active with | Private | Logical |
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Standby | Bus Name | Devices Connected | ||||
I2C Bus # | Bus ID | I2C Bus ID | ||||
| Power Only |
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0 | Y | - | 0 | IPMB | Hot Swap Controllers, IPMB Aux | |
connector, LCD Module | ||||||
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1 | Y | - | 2 | PCI | PCI Bus slots | |
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| PCA9555, LM93 (2), LM75, FRU, | |
2 | Y | 2 | 5 | IO | Power Distribution Board, Power | |
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| Supply Units (2) | |
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3 | N | 3 | 7 | CS | XMB (4), FC module, NB, PXH, | |
Intel® IOP332 Storage I/O Processor | ||||||
4 | Y | 4 | 9 | Processors | Processors (4) | |
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5 | Y | 5 | B | NIC | ||
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5.6.2Keyboard Controller Style (KCS)/Low Pin Count (LPC) Bus
The BMC has three KCS interface ports as described in the IPMI 2.0 specification. These interfaces are used to communicate SMI handling for error logging, BIOS POST, utility access and power management communication. The BMC also acts as a bridge between the SMS and IPMB interfaces.
5.6.3Inter-Chassis Management Bus (ICMB)
The Intelligent Chassis Management Bus (ICMB) defines a
38 | Revision 1.0 |
| Intel order number |