Server Management | Intel® Server Board Set SE8500HW4 |
5.4.2FRB2
The BIOS requests the BMC to start a second
If the FRB2 timer expires and the BIOS is configured with reset as the action to take on the timeout, the BMC will log an FRB2 timeout event with the last POST code generated and reset the system. By default the BSP processor will not be disabled on an FRB2 timeout. There is a BIOS option to disable the processor in an FRB2 timeout, but since this timeout may not be a processor failure, the default behavior is to only reset the system. If during the next boot the BIOS can determine that the last boot failure was processor related, the BIOS requests the BMC to disable the BSP and reset the system.
5.5Reset Control
Reset circuitry on the Mainboard is aware of resets from several sources and determines the proper reset sequence for the different types of resets. Table 13 defines all the reset sources and the actions taken by the system.
Table 13. System Reset Sources and Actions
Reset Source | System Reset? | BMC Reset? |
Standby power comes up | No (no DC power) | Yes |
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Main system power comes up | Yes | No |
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Reset button pushed | Yes | No |
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Warm reset | Yes | No |
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Set processor state or chasis control command | Yes | No |
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Watchdog timer configured for reset | Yes | No |
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FRB3 timeout | Yes | No |
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PEF action | Optional | No |
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Exit BMC firmware update mode | No | Yes |
5.5.1Front Panel Reset
The reset button is a momentary contact button on the front panel. It is routed through the front panel connector to the BMC, which monitors and
If secure mode is enabled, or the button is forced protected, the reset button does not reset the system, and a platform security violation attempt event message is logged. The reset button is also disabled in sleep mode.
5.5.2Warm Reset
A warm reset does not remove power from the system and is usually triggered by software or from the ICH5 (e.g. when
36 | Revision 1.0 |
| Intel order number |