APPENDIX D

GATESn

Pulse width measurement status bit n = 0,1,2

 

This bit is read only which indicates the status of the pulse

 

width measurement state machine. “1” means the measure

 

ment is in process; “0” means the measurement is complete.

CLK_SEL1 & 0 Counter internal clock select register

This clock is for counter 0 to 2 internal clock source.

The register sets the frequency of internal clock source of counter 0 to counter 2.

Table D-18: Table for CLK_SEL1 to CLK_SEL0 register

CLK_SEL1

 

 

CLK_SEL0

 

 

 

 

 

 

 

Meaning

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

0

 

 

 

 

 

 

 

Internal clock is 10MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0

 

 

 

1

 

 

 

 

 

 

 

Internal clock is 1MHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

0

 

 

 

 

 

 

 

Internal clock is 100KHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

 

 

 

1

 

 

 

 

 

 

 

Internal clock is 10KHz

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

D.15 Digital I/O registers — Write/Read BASE+28

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Table D-19: Register for Digital I/O

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Base Add.

15

14

13

12

11

10

9

 

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

Digital Output

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

28

DO15

DO14

DO13

DO12

DO11

DO10

DO9

 

DO8

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

Digital Input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DO15

DO14

DO13

DO12

DO11

DO10

DO9

 

DO8

DO7

DO6

DO5

DO4

DO3

DO2

DO1

DO0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

The PCI-1712/1712L provides 16 digital I/O channels. Each group of 8 channels can be defined as both input or output channels. You can configure digital input/output by setting the digital I/O configuration register. Refer to next section for more details.

DO15 to DO0

Digital output data register

DO0 is the least significant bit (LSB) of the digital output data.

DO15 is the most significant bit (MSB) of the digital output data.

Advantech Co., Ltd.

– 99 –

PCI-1712/1712L User’s Manual

www.advantech.com

 

 

Page 110 Page 112
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Image 111
Konica Minolta PCI-1712L Digital I/O registers Write/Read BASE+28, GATESn Pulse width measurement status bit n = 0,1,2
Page 110 Page 112

PCI-1712L, PCI-1712 specifications

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