1 MS/s, 12-bit, 16-ch High- Speed Multifunction Card
PCI-1712/1712L Users manual
Hardware Installation
Driver Installation
Verifying your Installation
PCI-1712/1712L Quick Start
Device Installation
Printed in Taiwan
2nd Edition
March
Copyright
2. Installation
Contents
3. Signal Connections
1. Introduction
Appendix B. Block Diagram
Appendix A. Specification
6. Calibration
Appendix C. Screw-terminal Board
Digital I/O registers - Write/Read BASE+28
Digital I/O configuration registers - Write/Read BASE+2A
D/A Channel Data for Continuous Output Operation Mode
Figures
Figure 6-6 A/D Calibration Procedure
Figure 6-5 A/D Calibration Procedure
Figure 6-7 A/D Calibration Procedure
Figure 6-14 Adjusting registers
Tables
Table D-21 Register for digital I/O configuration
Table D-20 Register for digital I/O configuration
Table D-22 Register for calibration command
Table D-23 Calibration command
Page
1. Introduction
1.1 Features
Chapter1
PCI-1712 1 MS/s High-Speed Multifunction Card
Chapter
q Wiring cable
1.2 Installation Guide
q Wiring board
q PCI-1712/1712L DAS card q PCI-1712/1712L User’s Manual
Chapter
Figure 1-1 Installation Flow Chart
PCI-1712/1712L User’s Manual
Wiring Cable
1.3 Accessories
Wiring Boards
PCI-1712/1712L User’s Manual
Chapter
Chapter2
2. Installation
2.1 Unpacking
Figure 2-1 The Setup Screen of Advantech Automation Software
2.2 Driver Installation
Figure 2-2 Different options for Driver Setup
2.3 Hardware Installation
Step 2 Remove the cover of your computer
Figure 2-3 The device name listed on the Device Manager
Figure 2-4 The Advantech Device Installation utility program
2.4 Device Setup & Configuration
Figure 2-5 The I/O Device Installation dialog box
Setting Up the Device
Figure 2-6 The “Devices Found” dialog box
Figure 2-7 The Device Setting dialog box
Configuring the Device
you will get a output voltage range
By inputting an external reference voltage xV, where 0=x=10
0 to
for unipolar
Figure 2-9 Analog Input tab on the Device Test dialog box
2.5 Device Testing
Testing Analog Input Function
Figure 2-11 Analog Output tab on the Device Test dialog box
Figure 2-10 Analog Input tab on the Device Test dialog box
Testing Analog Output Function PCI-1712 only
Testing Digital Input Function
Figure 2-13 Digital Output tab on the Device Test dialog box
Figure 2-12 Digital Input tab on the Device Test dialog box
Testing Digital Output Function
Testing Counter Function
configure the Pulse Frequency by the scroll bar right below it
Figure 2-14 Digital output tab on the Device Test dialog box
3.2 I/O Connector
3. Signal Connections
3.1 Overview
Chapter3
Pins 20, 22~25, 54, 56~59 are not defined on PCI-1712L
Figure 3-1 I/O connector pin assignments for the PCI-1712/1712L
PCI-1712/1712L User’s Manual
Signal Name
Table 3-1 I/O Connector Signal Description Part
Direction
Description
Signal Name
Table 3-1 I/O Connector Signal Description Part
Reference
Direction
Signal Name
Table 3-1 I/O Connector Signal Description Part
Direction
Description
Figure 3-2 Single-ended input channel connection
3.3 Analog Input Connections
Single-ended Channel Connections
Differential Channel Connections
Figure 3-3 Differential input channel connection - ground reference
signal source
source
Figure 3-4 Differential input channel connection - floating signal
Figure 3-5 Analog output connections
3.4 Analog Output Connections
3.5 Field Wiring Considerations
Chapter4
4. Software Overview
4.1 Programming Choices
q Visual C++ q Visual Basic q Delphi q C++ Builder
4.2 DLL Driver Programming Roadmap
q Analog Iutput Function Group q Analog Output Function Group
q Temperature Measurement Function Group q Alarm Function Group
q Digital Input/Output Function Group q Counter Function Group
q Port Function Group q Communication Function Group
PCI-1712/1712L User’s Manual
Chapter
5. Principles of Operation
5.1 Analog Input Features
Chapter5
Table 5-1 Gains and Analog Input Range
q Single Value Acquisition Mode
Figure 5-2 Delay-Trigger Acquisition Mode
Figure 5-1 Post-Trigger Acquisition Mode
Figure 5-3 About-Trigger Acquisition Mode
w Internal A/D sample clock with 16-bit Counter
Figure 5-4 Pre-Trigger Acquisition Mode
w Software trigger w External digital TTL trigger, and
Figure 5-5 PCI-1712/1712L Sample Clock Source
Table 5-3 The corresponding Full Scale values for various Input
Table 5-2 Analog Input Data Format
Voltage Ranges
q Analog Threshold Trigger
5.2 Analog Output Features
channel
Chapter
Table 5-4 Analog Output Data Format
5.3 Digital I/O Features
Table 5-5 The corresponding Full Scale values for various Output
Analog Output Data Format
5.4 Counter/Timer Features
q Logic-low external gate input
q Event counting
Chapter
Chapter
Chapter
Figure 5-6 Frequency measurement
dl= inportaddr21712+0x1c
Chapter
Read low byte
dh= inportaddr21712+0x1c8
Chapter
65535-50000/1K = 15.535 sec
Figure 5-7 Pulse width measurement
CNT2’s gate input is low
Chapter
Show the duty ratio of positive
Chapter
Chapter6
6. Calibration
6.1 VR Assignment
Figure 6-1 PCI-1712/1712L VR1 & TP5
6.2 A/D Calibration
6.3 D/A Calibration
Figure 6-2 Selecting the device you want to calibrate
6.4 Calibration Utility
Figure 6-4 Auto A/D Calibration Dialog Box
Figure 6-3 Warning message before start calibration
A/D channel Auto-Calibration
Figure 6-6 A/D Calibration Procedure
Figure 6-5 A/D Calibration Procedure
Step 5 The first A/D calibration procedure is enabled Fig
Step 6 The second A/D calibration procedure is enabled Fig
Figure 6-8 A/D Calibration is finished
Figure 6-7 A/D Calibration Procedure
Step 7 The third A/D calibration procedure is enabled Fig
Step 8 Auto-calibration is finished. See fig
Figure 6-10 Calibrating D/A Channel
Figure 6-9 Range Selection in D/A Calibration
Step 10 D/A channel 0 calibration is enabled Fig
Figure 6-12 D/A Calibration is finished
Figure 6-11 Calibrating D/A Channel
Step 11 D/A channel 1 calibration is enabled Fig
Step 12 Auto-calibration is finished Fig
A/D channel Manual-Calibration
Figure 6-13 Selecting Input Rage in Manual A/D Calibration panel
Figure 6-14 Adjusting registers
Choosing Output Voltage
Figure 6-15 & Figure 6-16 Selecting D/A Range and
D/A channel Manual-Calibration
Figure 6-17 Adjusting registers
PCI-1712/1712L User’s Manual
Chapter
Appendix A
A. Specification
PCI-1712 User’s Manual
Analog Output PCI-1712 only
APPENDIX A
Digital Input /Output
PCI-1712/1712L User’s Manual
General
Counter/Timer
PCI-1712/1712L User’s Manual
APPENDIX A
Appendix B
B. Block Diagram
PCI BUS
A I T R G A O T R G
PCI-1712/1712L User’s Manual
APPENDIX B
C. Screw-terminal Board
C. 2 Features
C. 1 Introduction
AppendixC
Figure C-2 CN2 pin assignments for the PCLD-8712
C.4 Pin Assignment
APPENDIX C
PCI-1712/1712L User’s Manual
C.5 Single-ended Connections
f3dB = 2π RAn+RAn+1 CDn
C.6 Differential Connections
RDn RAn+RAn+1+RDn
AppendixD
D. Register Structure and Format
D.1 Overview
D.2 I/O Port Address Map
APPENDIX D
Table D-1 PCI-1712/1712L register format Part
PCI-1712/1712L User’s Manual
Table D-1 PCI-1712/1712L register format Part
APPENDIX D
Table D-1 PCI-1712/1712L register format Part
APPENDIX D
PCI-1712/1712L User’s Manual
D.4 Channel and A/D data - Read BASE +
D.3 A/D Single Value Acquisition - Write BASE+0
Table D-2 Register for channel number and A/D data
Table D-3 Register for A/D channel range setting
D.5 A/D Channel Range Setting - Write BASE+2
Table D-4 Gain Codes for the PCI-1712/1712L
D.6 MUX Control - Write BASE+4
Table D-5 Register for multiplexer control
STR3 ~ STR0
APPENDIX D
Write/Read BASE+6
D.7 A/D Control/Status Register
Table D-6 Register for A/D control/status
ADM2 ~ ADM0
This bit is used to select the A/D sample clock source
Table D-7 Analog Input Acquisition Mode
Table D-8 Register for clear interrupt and FIFO
D.8 Clear interrupt and FIFO - Write BASE+8
Clear interrupt
Table D-9 Register for interrupt and FIFO status
D. 9 Interrupt and FIFO status - Read BASE+8
Table D-10 Register for D/A control
D.10 D/A control/status register - Write/Read BASE+A
DA1U/B
Table D-11 Analog output operation mode
D/A channel 1 unipolar or bipolar output
DACLK
Table D-12 Register for D/A channel 0/1 data
D.11 D/A Channel 0/1 Data - Write BASE+C/E
Table D-13 Register for 82C54 counter chip
D.12 82C54 Counter Chip 0 - Write/Read BASE+10 to
Table D-14 Register for 82C54 counter chip
D.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E
Table D-15 Register for counter gate and clock control/status
D.14 Counter gate and clock control/status - Write/ Read BASE+20 to
Table D-16 Table of Cn1 to Cn0 register
Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1
Counter clock edge control register n = 0,1,2
Table D-17 Table of Gn1 to Gn0 register
Counter clock set register n = 0,1,2
Gn1 to Gn0 Counter gate source control register n = 0,1,2
Counter gate polarity control register n = 0,1,2
Table D-18 Table for CLKSEL1 to CLKSEL0 register
D.15 Digital I/O registers - Write/Read BASE+28
Table D-19 Register for Digital I/O
D.17 Calibration command registers - Write BASE+2C
D.16 Digital I/O configuration registers - Write/Read BASE+2A
Table D-20 Register for digital I/O configuration
Table D-22 Register for calibration command
CM3 to CM0 Calibration command
Table D-23 Calibration command
D7 to D0
Calibration data
DA11 TO DA0 D/A data
Table D-24 Register for D/A channel data
