APPENDIX D

D.14 Counter gate and clock control/status Write/ Read BASE+20 to 26

Table D-15: Register for counter gate and clock control/status

Base Add.

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

Counter 0 gate and clock control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GR0

GQ0

GP0

G01

G00

CQ0

CP0

C01

C00

 

 

 

 

 

 

 

 

 

20

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter 0 gate and clock status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAT-

CLK0

OUT0

GAT-

GQ0

GP0

G01

G00

CQ0

CP0

C01

C00

 

 

 

 

 

 

 

 

 

 

 

 

ES0

E0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

Counter 1 gate and clock control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GR1

GQ1

GP1

G11

G10

CQ1

CP1

C11

C10

 

 

 

 

 

 

 

 

 

22

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter 1 gate and clock status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAT-

CLK1

OUT1

GAT-

GQ1

GP1

G11

G10

CQ1

CP1

C11

C10

 

 

 

 

 

 

 

 

 

 

 

 

ES1

 

 

E1

 

 

 

 

 

 

 

 

 

W

 

 

 

 

 

Counter 2 gate and clock control

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GR2

GQ2

GP2

G21

G20

CQ2

CP2

C21

C20

 

 

 

 

 

 

 

 

 

24

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter 2 gate and clock status

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GAT-

CLK2

OUT2

GAT-

GQ2

GP2

G21

G20

CQ2

CP2

C21

C20

 

 

 

 

 

 

 

 

 

 

 

 

ES2

 

 

E2

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Counter internal clock source select register

 

 

 

 

 

W

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CLK_-

CLK_-

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

26

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SEL1

SEL0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

R

 

 

 

 

 

 

 

N/A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Cn1 to Cn0

Counter clock source control register n = 0,1,2

 

 

Table D-16 : Table of Cn1 to Cn0 register

 

 

 

 

Cn1

 

Cn0

Meaning

 

 

 

 

0

 

0

Clock is set by CQn

 

 

 

 

0

 

1

Clock comes from internal clock

 

 

 

 

1

 

0

Clock comes from external clock

 

 

 

 

1

 

1

Clock comes from previous counter’s out

 

 

 

 

[Cn1: Cn0] = [0, 0], write CQn to set the counter clock. Refer to CQn description.

[Cn1: Cn0] = [0, 1], The internal clock is generated by an on- board oscillator.

[Cn1: Cn0] = [1, 0], External clock is on connector CNTn_CLK (n = 0, 1, 2).

[Cn1: Cn0] = [1, 1], The clock source of every counter

PCI-1712/1712L User’s Manual

– 96 –

Advantech Co., Ltd.

 

 

www.advantech.com

Page 108
Image 108
Konica Minolta PCI-1712L user manual Cn1 to Cn0 Counter clock source control register n = 0,1,2

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