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Konica Minolta PCI-1712L user manual Field Wiring Considerations

Models: PCI-1712L PCI-1712

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Chapter 3

3.5 Field Wiring Considerations

When you use the PCI-1712/1712L to acquire data from outside, noises in the environment might significantly affect the accuracy of your measurements if due cautions are not taken. The following measures will be helpful to reduce possible interference running signal wires between signal sources and the PCI-1712/1712L.

•The signal cables must be kept away from strong electromag- netic sources such as power lines, large electric motors, circuit breakers or welding machines, since they may cause strong electromagnetic interference. Keep the analog signal cables away from any video monitor, since it can significantly affect data acquisition system.

•If the cable travels through area with significant electromagnetic interference, you should adopt individually shielded, twisted- pair wires as the analog input cable. This type of cable have its signal wires twisted together and shielded with a metal mesh. The metal mesh should only be connected to one point at the signal source ground.

•Avoid running the signal cables through any conduit that might have power lines in it.

•If you have to place your signal cable parallel to a power line that has a high voltage or high current running through it, try to keep a safe distance between them. Or you should place the signal cable at right angle to the power line to minimize the undesirable effect.

•The signals transmitted on the cable will be directly affected by the quality of the cable. In order to ensure best signal quality, we recommend that you use the PCL-10168 shielded cable.

PCI-1712/1712L User’s Manual	– 28 –	Advantech Co., Ltd.
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Konica Minolta PCI-1712L user manual Field Wiring Considerations

Contents

PCI-1712/1712L Users manual 1 MS/s, 12-bit, 16-ch High- Speed Multifunction CardDriver Installation Hardware InstallationVerifying your Installation PCI-1712/1712L Quick StartDevice Installation 2nd Edition Printed in TaiwanMarch CopyrightContents 2. Installation3. Signal Connections 1. IntroductionAppendix A. Specification Appendix B. Block Diagram6. Calibration Appendix C. Screw-terminal BoardD/A Channel Data for Continuous Output Operation Mode Digital I/O configuration registers - Write/Read BASE+2ADigital I/O registers - Write/Read BASE+28 Figures Figure 6-5 A/D Calibration Procedure Figure 6-6 A/D Calibration ProcedureFigure 6-7 A/D Calibration Procedure Figure 6-14 Adjusting registersTables Table D-20 Register for digital I/O configuration Table D-21 Register for digital I/O configurationTable D-22 Register for calibration command Table D-23 Calibration commandPage 1.1 Features 1. IntroductionChapter1 PCI-1712 1 MS/s High-Speed Multifunction CardChapter 1.2 Installation Guide q Wiring cableq Wiring board q PCI-1712/1712L DAS card q PCI-1712/1712L User’s ManualChapter Figure 1-1 Installation Flow ChartPCI-1712/1712L User’s Manual Wiring Cable 1.3 AccessoriesWiring Boards Chapter PCI-1712/1712L User’s ManualChapter2 2. Installation2.1 Unpacking 2.2 Driver Installation Figure 2-1 The Setup Screen of Advantech Automation Software2.3 Hardware Installation Figure 2-2 Different options for Driver SetupStep 2 Remove the cover of your computer Figure 2-3 The device name listed on the Device Manager 2.4 Device Setup & Configuration Figure 2-4 The Advantech Device Installation utility programFigure 2-5 The I/O Device Installation dialog box Setting Up the DeviceFigure 2-6 The “Devices Found” dialog box Figure 2-7 The Device Setting dialog boxConfiguring the Device By inputting an external reference voltage xV, where 0=x=10 you will get a output voltage range0 to for unipolarFigure 2-9 Analog Input tab on the Device Test dialog box 2.5 Device TestingTesting Analog Input Function Figure 2-10 Analog Input tab on the Device Test dialog box Figure 2-11 Analog Output tab on the Device Test dialog boxTesting Analog Output Function PCI-1712 only Testing Digital Input FunctionFigure 2-12 Digital Input tab on the Device Test dialog box Figure 2-13 Digital Output tab on the Device Test dialog boxTesting Digital Output Function Testing Counter FunctionFigure 2-14 Digital output tab on the Device Test dialog box configure the Pulse Frequency by the scroll bar right below it3. Signal Connections 3.2 I/O Connector3.1 Overview Chapter3Pins 20, 22~25, 54, 56~59 are not defined on PCI-1712L Figure 3-1 I/O connector pin assignments for the PCI-1712/1712LPCI-1712/1712L User’s Manual Table 3-1 I/O Connector Signal Description Part Signal NameDirection DescriptionTable 3-1 I/O Connector Signal Description Part Signal NameReference DirectionTable 3-1 I/O Connector Signal Description Part Signal NameDirection Description3.3 Analog Input Connections Figure 3-2 Single-ended input channel connectionSingle-ended Channel Connections Differential Channel Connectionssignal source Figure 3-3 Differential input channel connection - ground referenceFigure 3-4 Differential input channel connection - floating signal source3.4 Analog Output Connections Figure 3-5 Analog output connections3.5 Field Wiring Considerations Chapter4 4. Software Overview4.1 Programming Choices 4.2 DLL Driver Programming Roadmap q Visual C++ q Visual Basic q Delphi q C++ Builderq Temperature Measurement Function Group q Alarm Function Group q Analog Iutput Function Group q Analog Output Function Groupq Digital Input/Output Function Group q Counter Function Group q Port Function Group q Communication Function GroupChapter PCI-1712/1712L User’s Manual5.1 Analog Input Features 5. Principles of OperationChapter5 Table 5-1 Gains and Analog Input Rangeq Single Value Acquisition Mode Figure 5-1 Post-Trigger Acquisition Mode Figure 5-2 Delay-Trigger Acquisition ModeFigure 5-3 About-Trigger Acquisition Mode Figure 5-4 Pre-Trigger Acquisition Mode w Internal A/D sample clock with 16-bit CounterFigure 5-5 PCI-1712/1712L Sample Clock Source w Software trigger w External digital TTL trigger, andTable 5-2 Analog Input Data Format Table 5-3 The corresponding Full Scale values for various InputVoltage Ranges q Analog Threshold Trigger5.2 Analog Output Features channel Chapter 5.3 Digital I/O Features Table 5-4 Analog Output Data FormatTable 5-5 The corresponding Full Scale values for various Output Analog Output Data Format5.4 Counter/Timer Features q Logic-low external gate input q Event counting Chapter Chapter Figure 5-6 Frequency measurement ChapterChapter dl= inportaddr21712+0x1cRead low byte dh= inportaddr21712+0x1c8Chapter Figure 5-7 Pulse width measurement 65535-50000/1K = 15.535 secChapter CNT2’s gate input is lowChapter Show the duty ratio of positive6. Calibration Chapter66.1 VR Assignment Figure 6-1 PCI-1712/1712L VR1 & TP56.2 A/D Calibration 6.3 D/A Calibration 6.4 Calibration Utility Figure 6-2 Selecting the device you want to calibrateFigure 6-4 Auto A/D Calibration Dialog Box Figure 6-3 Warning message before start calibrationA/D channel Auto-Calibration Figure 6-5 A/D Calibration Procedure Figure 6-6 A/D Calibration ProcedureStep 5 The first A/D calibration procedure is enabled Fig Step 6 The second A/D calibration procedure is enabled FigFigure 6-7 A/D Calibration Procedure Figure 6-8 A/D Calibration is finishedStep 7 The third A/D calibration procedure is enabled Fig Step 8 Auto-calibration is finished. See figFigure 6-10 Calibrating D/A Channel Figure 6-9 Range Selection in D/A CalibrationStep 10 D/A channel 0 calibration is enabled Fig Figure 6-11 Calibrating D/A Channel Figure 6-12 D/A Calibration is finishedStep 11 D/A channel 1 calibration is enabled Fig Step 12 Auto-calibration is finished FigFigure 6-13 Selecting Input Rage in Manual A/D Calibration panel A/D channel Manual-CalibrationFigure 6-14 Adjusting registers Choosing Output Voltage Figure 6-15 & Figure 6-16 Selecting D/A Range andD/A channel Manual-Calibration Figure 6-17 Adjusting registers Chapter PCI-1712/1712L User’s ManualAppendix A A. SpecificationPCI-1712 User’s Manual APPENDIX A Analog Output PCI-1712 onlyDigital Input /Output PCI-1712/1712L User’s ManualCounter/Timer GeneralAPPENDIX A PCI-1712/1712L User’s ManualB. Block Diagram Appendix BPCI BUS A I T R G A O T R GAPPENDIX B PCI-1712/1712L User’s ManualC. 2 Features C. Screw-terminal BoardC. 1 Introduction AppendixCC.4 Pin Assignment Figure C-2 CN2 pin assignments for the PCLD-8712APPENDIX C PCI-1712/1712L User’s ManualC.5 Single-ended Connections f3dB = 2π RAn+RAn+1 CDn C.6 Differential ConnectionsRDn RAn+RAn+1+RDn D. Register Structure and Format AppendixDD.1 Overview D.2 I/O Port Address MapAPPENDIX D Table D-1 PCI-1712/1712L register format PartPCI-1712/1712L User’s Manual APPENDIX D Table D-1 PCI-1712/1712L register format PartTable D-1 PCI-1712/1712L register format Part APPENDIX DPCI-1712/1712L User’s Manual D.4 Channel and A/D data - Read BASE + D.3 A/D Single Value Acquisition - Write BASE+0Table D-2 Register for channel number and A/D data D.5 A/D Channel Range Setting - Write BASE+2 Table D-3 Register for A/D channel range settingD.6 MUX Control - Write BASE+4 Table D-4 Gain Codes for the PCI-1712/1712LTable D-5 Register for multiplexer control STR3 ~ STR0APPENDIX D D.7 A/D Control/Status Register Write/Read BASE+6Table D-6 Register for A/D control/status Analog input acquisition mode registerTable D-7 Analog Input Acquisition Mode This bit is used to select the A/D sample clock sourceTable D-8 Register for clear interrupt and FIFO D.8 Clear interrupt and FIFO - Write BASE+8Clear interrupt D. 9 Interrupt and FIFO status - Read BASE+8 Table D-9 Register for interrupt and FIFO statusD.10 D/A control/status register - Write/Read BASE+A Table D-10 Register for D/A controlTable D-11 Analog output operation mode DA1U/BD/A channel 1 unipolar or bipolar output DACLKD.11 D/A Channel 0/1 Data - Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataD.12 82C54 Counter Chip 0 - Write/Read BASE+10 to Table D-13 Register for 82C54 counter chipD.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E Table D-14 Register for 82C54 counter chipD.14 Counter gate and clock control/status - Write/ Read BASE+20 to Table D-15 Register for counter gate and clock control/statusTable D-16 Table of Cn1 to Cn0 register Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1Table D-17 Table of Gn1 to Gn0 register Counter clock edge control register n = 0,1,2Counter clock set register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2Counter gate polarity control register n = 0,1,2 Table D-18 Table for CLKSEL1 to CLKSEL0 register D.15 Digital I/O registers - Write/Read BASE+28Table D-19 Register for Digital I/O D.16 Digital I/O configuration registers - Write/Read BASE+2A D.17 Calibration command registers - Write BASE+2CTable D-20 Register for digital I/O configuration Table D-22 Register for calibration commandTable D-23 Calibration command CM3 to CM0 Calibration commandD7 to D0 Calibration dataTable D-24 Register for D/A channel data DA11 TO DA0 D/A data