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Konica Minolta PCI-1712L user manual 6.2 A/D Calibration

Models: PCI-1712L PCI-1712

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Chapter 6

6.2 A/D Calibration

Regular and proper calibration procedures ensure the maximum possible accuracy. It is easy to complete the A/D calibration proce- dure automatically (i.e. through software calibration) by executing the A/D calibration program AutoCali. Therefore, it is not necessary to adjust the hardware settings of the PCI-1712/1712L. However, the following calibration steps are also provided for your reference in case manual calibration is needed:

1.Adjust VR1 until the reference voltage on TP5 has reached +5.0000 V.

2.Set PCI-1712 to calibration mode, which will configure AI2 to +5 V, and AI0 to 0 V. (Write “1” in AI0_CAL at the register address BASE+6 bif7).

3.Adjust the PGA offset voltage. First, set the analog input voltage range of AI0 to ±10V. Adjust the PGA offset register (BASE+2C), and acquire a value from AI0 in single value acquisition mode.

Then switch the analog voltage range to ±1.25V to repeat the operation in this step again to acquire a value from AI0. Repeat this cycle several times. Meanwhile, adjust the PGA offset voltage until the AI0’s values become the same for both the analog input range ±10 V and ±1.25 V.

4.Adjust the gain value of the PGA. First, set the analog input voltage range of AI2 between 0 and 5V. Adjust the gain register (Base+2C), and then acquire the value for AI2 from single value

acquisition mode. Adjust the gain value of the PGA until the

subsequent AI2’s values converge within the Ox0ffe to

Ox0fff range.

5.Adjust the bipolar offset voltage. First, set the analog input range within ±2.5 V. Adjust the bipolar offset register (Base+2C), and then acquire the code from AI0 from single value acquisition mode. Adjust the bipolar offset voltage until the AI0’s code flickers around Ox0800.

6.Adjust unipolar offset voltage. First, set the analog input range within 0 and 5 V. Adjust the unipolar offset register (Base+2C), and then acquire the code for AI0 from single value acquisition

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Konica Minolta PCI-1712L user manual 6.2 A/D Calibration

Contents

PCI-1712/1712L Users manual 1 MS/s, 12-bit, 16-ch High- Speed Multifunction CardDriver Installation Hardware InstallationVerifying your Installation PCI-1712/1712L Quick StartDevice Installation 2nd Edition Printed in TaiwanMarch CopyrightContents 2. Installation3. Signal Connections 1. IntroductionAppendix A. Specification Appendix B. Block Diagram6. Calibration Appendix C. Screw-terminal BoardDigital I/O registers - Write/Read BASE+28 Digital I/O configuration registers - Write/Read BASE+2AD/A Channel Data for Continuous Output Operation Mode Figures Figure 6-5 A/D Calibration Procedure Figure 6-6 A/D Calibration ProcedureFigure 6-7 A/D Calibration Procedure Figure 6-14 Adjusting registersTables Table D-20 Register for digital I/O configuration Table D-21 Register for digital I/O configurationTable D-22 Register for calibration command Table D-23 Calibration commandPage 1.1 Features 1. IntroductionChapter1 PCI-1712 1 MS/s High-Speed Multifunction CardChapter 1.2 Installation Guide q Wiring cableq Wiring board q PCI-1712/1712L DAS card q PCI-1712/1712L User’s ManualPCI-1712/1712L User’s Manual Figure 1-1 Installation Flow ChartChapter Wiring Boards 1.3 AccessoriesWiring Cable Chapter PCI-1712/1712L User’s Manual2.1 Unpacking 2. InstallationChapter2 2.2 Driver Installation Figure 2-1 The Setup Screen of Advantech Automation Software2.3 Hardware Installation Figure 2-2 Different options for Driver SetupStep 2 Remove the cover of your computer Figure 2-3 The device name listed on the Device Manager 2.4 Device Setup & Configuration Figure 2-4 The Advantech Device Installation utility programFigure 2-5 The I/O Device Installation dialog box Setting Up the DeviceConfiguring the Device Figure 2-7 The Device Setting dialog boxFigure 2-6 The “Devices Found” dialog box By inputting an external reference voltage xV, where 0=x=10 you will get a output voltage range0 to for unipolarTesting Analog Input Function 2.5 Device TestingFigure 2-9 Analog Input tab on the Device Test dialog box Figure 2-10 Analog Input tab on the Device Test dialog box Figure 2-11 Analog Output tab on the Device Test dialog boxTesting Analog Output Function PCI-1712 only Testing Digital Input FunctionFigure 2-12 Digital Input tab on the Device Test dialog box Figure 2-13 Digital Output tab on the Device Test dialog boxTesting Digital Output Function Testing Counter FunctionFigure 2-14 Digital output tab on the Device Test dialog box configure the Pulse Frequency by the scroll bar right below it3. Signal Connections 3.2 I/O Connector3.1 Overview Chapter3PCI-1712/1712L User’s Manual Figure 3-1 I/O connector pin assignments for the PCI-1712/1712LPins 20, 22~25, 54, 56~59 are not defined on PCI-1712L Table 3-1 I/O Connector Signal Description Part Signal NameDirection DescriptionTable 3-1 I/O Connector Signal Description Part Signal NameReference DirectionTable 3-1 I/O Connector Signal Description Part Signal NameDirection Description3.3 Analog Input Connections Figure 3-2 Single-ended input channel connectionSingle-ended Channel Connections Differential Channel Connectionssignal source Figure 3-3 Differential input channel connection - ground referenceFigure 3-4 Differential input channel connection - floating signal source3.4 Analog Output Connections Figure 3-5 Analog output connections3.5 Field Wiring Considerations 4.1 Programming Choices 4. Software OverviewChapter4 4.2 DLL Driver Programming Roadmap q Visual C++ q Visual Basic q Delphi q C++ Builderq Temperature Measurement Function Group q Alarm Function Group q Analog Iutput Function Group q Analog Output Function Groupq Digital Input/Output Function Group q Counter Function Group q Port Function Group q Communication Function GroupChapter PCI-1712/1712L User’s Manual5.1 Analog Input Features 5. Principles of OperationChapter5 Table 5-1 Gains and Analog Input Rangeq Single Value Acquisition Mode Figure 5-1 Post-Trigger Acquisition Mode Figure 5-2 Delay-Trigger Acquisition ModeFigure 5-3 About-Trigger Acquisition Mode Figure 5-4 Pre-Trigger Acquisition Mode w Internal A/D sample clock with 16-bit CounterFigure 5-5 PCI-1712/1712L Sample Clock Source w Software trigger w External digital TTL trigger, andTable 5-2 Analog Input Data Format Table 5-3 The corresponding Full Scale values for various InputVoltage Ranges q Analog Threshold Trigger5.2 Analog Output Features channel Chapter 5.3 Digital I/O Features Table 5-4 Analog Output Data FormatTable 5-5 The corresponding Full Scale values for various Output Analog Output Data Format5.4 Counter/Timer Features q Logic-low external gate input q Event counting Chapter Chapter Figure 5-6 Frequency measurement ChapterChapter dl= inportaddr21712+0x1cRead low byte dh= inportaddr21712+0x1c8Chapter Figure 5-7 Pulse width measurement 65535-50000/1K = 15.535 secChapter CNT2’s gate input is lowChapter Show the duty ratio of positive6. Calibration Chapter66.1 VR Assignment Figure 6-1 PCI-1712/1712L VR1 & TP56.2 A/D Calibration 6.3 D/A Calibration 6.4 Calibration Utility Figure 6-2 Selecting the device you want to calibrateA/D channel Auto-Calibration Figure 6-3 Warning message before start calibrationFigure 6-4 Auto A/D Calibration Dialog Box Figure 6-5 A/D Calibration Procedure Figure 6-6 A/D Calibration ProcedureStep 5 The first A/D calibration procedure is enabled Fig Step 6 The second A/D calibration procedure is enabled FigFigure 6-7 A/D Calibration Procedure Figure 6-8 A/D Calibration is finishedStep 7 The third A/D calibration procedure is enabled Fig Step 8 Auto-calibration is finished. See figStep 10 D/A channel 0 calibration is enabled Fig Figure 6-9 Range Selection in D/A CalibrationFigure 6-10 Calibrating D/A Channel Figure 6-11 Calibrating D/A Channel Figure 6-12 D/A Calibration is finishedStep 11 D/A channel 1 calibration is enabled Fig Step 12 Auto-calibration is finished FigFigure 6-13 Selecting Input Rage in Manual A/D Calibration panel A/D channel Manual-CalibrationFigure 6-14 Adjusting registers D/A channel Manual-Calibration Figure 6-15 & Figure 6-16 Selecting D/A Range andChoosing Output Voltage Figure 6-17 Adjusting registers Chapter PCI-1712/1712L User’s ManualPCI-1712 User’s Manual A. SpecificationAppendix A APPENDIX A Analog Output PCI-1712 onlyDigital Input /Output PCI-1712/1712L User’s ManualCounter/Timer GeneralAPPENDIX A PCI-1712/1712L User’s ManualB. Block Diagram Appendix BPCI BUS A I T R G A O T R GAPPENDIX B PCI-1712/1712L User’s ManualC. 2 Features C. Screw-terminal BoardC. 1 Introduction AppendixCC.4 Pin Assignment Figure C-2 CN2 pin assignments for the PCLD-8712APPENDIX C PCI-1712/1712L User’s ManualC.5 Single-ended Connections RDn RAn+RAn+1+RDn C.6 Differential Connectionsf3dB = 2π RAn+RAn+1 CDn D. Register Structure and Format AppendixDD.1 Overview D.2 I/O Port Address MapPCI-1712/1712L User’s Manual Table D-1 PCI-1712/1712L register format PartAPPENDIX D APPENDIX D Table D-1 PCI-1712/1712L register format PartPCI-1712/1712L User’s Manual APPENDIX DTable D-1 PCI-1712/1712L register format Part Table D-2 Register for channel number and A/D data D.3 A/D Single Value Acquisition - Write BASE+0D.4 Channel and A/D data - Read BASE + D.5 A/D Channel Range Setting - Write BASE+2 Table D-3 Register for A/D channel range settingD.6 MUX Control - Write BASE+4 Table D-4 Gain Codes for the PCI-1712/1712LTable D-5 Register for multiplexer control STR3 ~ STR0APPENDIX D D.7 A/D Control/Status Register Write/Read BASE+6Table D-6 Register for A/D control/status Analog input acquisition mode registerTable D-7 Analog Input Acquisition Mode This bit is used to select the A/D sample clock sourceClear interrupt D.8 Clear interrupt and FIFO - Write BASE+8Table D-8 Register for clear interrupt and FIFO D. 9 Interrupt and FIFO status - Read BASE+8 Table D-9 Register for interrupt and FIFO statusD.10 D/A control/status register - Write/Read BASE+A Table D-10 Register for D/A controlTable D-11 Analog output operation mode DA1U/BD/A channel 1 unipolar or bipolar output DACLKD.11 D/A Channel 0/1 Data - Write BASE+C/E Table D-12 Register for D/A channel 0/1 dataD.12 82C54 Counter Chip 0 - Write/Read BASE+10 to Table D-13 Register for 82C54 counter chipD.13 82C54 counter chip 1 - Write/Read BASE+18 to 1E Table D-14 Register for 82C54 counter chipD.14 Counter gate and clock control/status - Write/ Read BASE+20 to Table D-15 Register for counter gate and clock control/statusTable D-16 Table of Cn1 to Cn0 register Cn1 Cn0 = 1, 0, External clock is on connector CNTnCLK n = 0, 1Table D-17 Table of Gn1 to Gn0 register Counter clock edge control register n = 0,1,2Counter clock set register n = 0,1,2 Gn1 to Gn0 Counter gate source control register n = 0,1,2Counter gate polarity control register n = 0,1,2 Table D-19 Register for Digital I/O D.15 Digital I/O registers - Write/Read BASE+28Table D-18 Table for CLKSEL1 to CLKSEL0 register D.16 Digital I/O configuration registers - Write/Read BASE+2A D.17 Calibration command registers - Write BASE+2CTable D-20 Register for digital I/O configuration Table D-22 Register for calibration commandTable D-23 Calibration command CM3 to CM0 Calibration commandD7 to D0 Calibration dataTable D-24 Register for D/A channel data DA11 TO DA0 D/A data